JPH04302B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a data processing device equipped with an editing processing (hereinafter referred to as EDIT) instruction execution mechanism.
Concerning the execution control method of the EDIT command. With recent advances in computer systems,
In various fields, data is increasingly being processed by computers, and as the amount of data processed in each field increases, it is expected that the processing power of computer systems that process that data will improve. It's starting to feel like this. In this situation, especially in the field of business calculations, for example, COBOL
Looking at the usage frequency of the instructions used in the computer system, such as MIX), the ratio of EDIT instructions is large, for example, around 10%, and even if some hardware is added, the processing of the EDIT instructions There has been a growing demand to improve the throughput of the entire computer system by improving efficiency. [Prior Art] The EDIT command used in computer systems, especially office computer systems, is used, for example, when printing out source digits expressed in decimal numbers.
It is used when converting to a specific format, and its command format is indicated by the SS type. That is,

[Means for solving problems]

This purpose is achieved by directing the editing content. "This purpose consists of data length L, operand 1 (OP1), and operand 2 (OP2). The above operand 1 (OP1) specifies the editing pattern character, and the above operand 2 (OP2)
Indicates the source digit, and the data length L specifies the operand 1 used for the editing process.
(OP1) specifies the data length n bytes, and based on the n-byte editing pattern character specified by operand 1 (OP1) above, the corresponding operand 2
In a data processing device equipped with an execution mechanism for the editing processing (EDIT) command that performs editing processing on the source digit specified by (OP2), is there a page cross between operand 1 (OP1) and operand 2 (OP2)? An address check mechanism 5 detects whether or not the source digit is required, and each time the operand 1 (OP1) is read by one byte, it is checked whether or not the source digit is necessary, and when the source digit is required, it is indicated that the source digit has been read. Equipped with a mechanism for setting flag bit (F-FL) 6,
In the address check mechanism 5, the operand 1
When it is detected that operand 2 (OP1) and operand 2 (OP2) do not cross pages, the edit pattern characters that instruct the editing content of operand 1 (OP1) are transferred from main storage unit (MSU) 1 to the After reading the n bytes specified by the data length L and performing the editing process specified by the edit pattern character of operand 1 (OP1) n times, the editing process target for the n bytes of the already processed edit pattern character is The editing process result 4 is not stored in the main storage unit (MSU) 1 only when the flag bit (F-FL) 6 indicating whether the source digit has been read is checked and it is detected that the source digit has not been read. , the address check mechanism 5 performs an access exception check on the part of the source digit indicated by the operand 2 (OP2).
This is achieved by the EDIT instruction execution control method. [Operation] That is, according to the present invention, if there is no page cross in both OP1 and OP2 when executing the EDIT instruction,
Since execution of the editing process (EDIT) is started without performing an access exception check on the source digit, the overhead for the access exception check can be reduced. However, after executing the n-byte editing process (EDIT) indicated by the data length L of the EDIT command above, check that the source digit is not being read {Flag bit (F-FL) 6 described later
} and the source digit is not being read {i.e., the flag bit (F-FL)
6 is “off”), it is necessary to check the access exception for the unread source digital part {that is, OP2}, but by setting n above to an appropriate value, checking is not necessary. It is possible to reduce the probability of [Examples] Examples of the present invention will be described in detail below with reference to the drawings.
FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows an EDIT
This is a flowchart showing the operation when an instruction is executed. The same reference numerals as in FIGS. 3 and 4 indicate the same objects or processes, and the flag bit (F-FL) 6, and Circuit A70, 71,
Steps 14 to 18 in FIG. 2 are the functional blocks and operational steps necessary to carry out the present invention. First, as in the conventional method, when the execution of the EDIT instruction is started, the address check section 5 performs a page cross check on the access addresses of OP1 and OP2.
If a page cross occurs in any of OP2, an access exception check will occur. Figure 2,
(See step 10) In the present invention, if there is no page cross in either OP1 or OP2, OP1 and OP2 are accessed immediately, and the EDIT control circuit 3 performs the above-mentioned editing process (EDIT). , is unique in that it is executed for one byte. (See step 13 in FIG. 2.) Then, the necessity of a source digit is checked for each byte of the pattern, and if a source digit is necessary, the source digit is read from the main storage unit (MSU) 1, and the flag bit ( If the flag bit (F-FL) 6 is set and the pattern does not require a source digit, such as the above-mentioned significant digit start character (SS) or digit selection character (DS), the flag bit (F-FL) 6 is turned off. and enters editing processing (EDIT) for the next pattern. Then, the above-mentioned editing process (EDIT) and source digit necessity check are repeated until processing of all n bytes specified by the EDIT command is completed. (Figure 2, Step
13 to 16) When the above editing process (EDIT) is completed for the n-byte pattern specified by the above EDIT command, the above flag bit (F-FL) 6 is set.
is on, all source digits required for the editing process (EDIT) are read out, and access exceptions, etc. are checked in the address check section 5 at the time of reading, so the AND circuit A70 checks the logic. A control signal (data store signal) obtained by taking the product controls the editing processing (EDIT) result of n bytes stored in the D-REG 4 to be stored in the main storage unit (MSU) 1. If the above flag bit (F-FL) 6 is off, in the editing process (EDIT),
This means that the source digit has never been read, so the address check unit 5 performs an access exception check for OP2 that has not yet been read using the control signal (pretest signal) that is ANDed in the AND circuit A71. Control the way you do it. (See Figure 2, 17, 18) In this way, in the present invention, when the editing process (EDIT) of n bytes specified by the EDIT command is completed, the flag bit (F-FL) indicating whether or not the source digit has been read is set. ) 6, the feature is that the access exception check for the source digit is performed only when the source digit has never been read.
By appropriately setting the value of , the probability of requiring an access exception check for the source digit can be reduced. [Effects of the Invention] As explained in detail below, the EDIT of the present invention
In the instruction control method, when an EDIT instruction is executed, if the address check mechanism detects that neither OP1 nor OP2 has a page cross, access to the source digit is disabled regardless of whether the source digit is read or not. Since execution of editing processing (EDIT) is started without performing an exception check, the overhead for the access exception check can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a flowchart showing the operation when the present invention is implemented and an EDIT command is executed, and Fig. 3 is a conventional technique. FIG. 4 is a block diagram showing the relevant parts when executing the EDIT command, and FIG. 4 is a flowchart showing the operation of the EDIT command according to the prior art. In the drawing, 1 is the main storage unit (MSU), 2 is S-REG, 3 is EDIT control circuit, 4 is D-REG,
5 is an address check section, 6 is a flag bit (F
-FL), 70, 71 are AND circuits (A), 10~
Reference numeral 18 indicates each step of the editing processing (EDIT) operation.

Claims (1)

[Claims] 1 Data length L and operand 1 (OP1)
and operand 2 (OP2), the above operand 1 (OP1) specifies the editing pattern character, the above operand 2 (OP2) specifies the source digit, and the above data length L is used for the above editing process. Data length n of operand 1 (OP1)
Based on the n-byte edit pattern character specified by operand 1 (OP1) above,
In a data processing device equipped with an execution mechanism for an editing processing (EDIT) instruction that performs editing processing on a source digit indicated by a corresponding operand 2 (OP2), the above operand 1 (OP1) and operand 2 are
The address check mechanism 5 detects whether a page cross occurs in (OP2), and checks whether or not a source digit is necessary every time one byte of operand 1 (OP1) is read. A mechanism for setting a flag bit (F-FL) 6 indicating that the source digit has been read is provided, and the address check mechanism 5 detects that operand 1 (OP1) and operand 2 (OP2) have a page cross. If it is detected that there is no edit pattern character indicating the editing content of the operand 1 (OP1), the n bytes indicated by the data length L are read from the main storage unit (MSU) 1, and
After performing the editing process specified by the edit pattern character of operand 1 (OP1) n times, the flag bit () indicating whether or not the source digit to be edited is read out for the already processed n-byte edit pattern character is set. F-FL) 6 and only when it is detected that the source digit has not been read, the editing processing result 4 is not stored in the main storage unit (MSU) 1, but the operand 2 (OP2) instructs it. An editing processing instruction execution control method characterized in that the address check mechanism 5 performs an access exception check on a source digit part.