JPH0430422A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the yield of production of the high speed and high density integrated circuit consisting of a microscopic MOS transistor and the like requiring a shallow impurity region by a method wherein an excellent ohmic contact is formed on the connection part between a semiconductor substrate and a wiring. CONSTITUTION:A silicon substrate 1 is heat-treated (first heat treatment) in the inert atmosphere such as nitrogen, for example. As a result, a titanium silicide (TiSi2), for example, is grown by allowing a metal layer 6 to react with the silicon substrate 1 and a crystalline silicon layer 4. Then, phosphorus (P) is doped, as n-type impurities, on the polycrystalline layer 4 by conducting an ion-implanting method, for example. Then, the silicon substrate 1 is heat- treated (second heat treatment). As a result, phosphorus (P) is diffused on the substrate 1, and a shallow n-type impurity region 2 is formed. Then, an insulating layer 10 is deposite on the whole surface of the substrate 1, a contact hole, to be used to expose the silicon layer 4 to the polycrystalline silicon layer 4 on the insulating layer 10, in formed, and the layer 10 is connected to the polycrystalline silicon layer 4. A wiring layer 5, consisting of aluminum (Al) is formed, and an n-channel MOS transistor is completed.

Description

[Detailed Description of the Invention] [Summary] Heat treatment for removing natural oxide film that inhibits solid-phase diffusion to form shallow impurity regions for high-density, high-performance semiconductor integrated circuits that require fine impurity regions. In the process, by suppressing the reaction between the metal layer provided to remove the natural oxide film and the underlying semiconductor substrate, the shallow impurity region is prevented from being destroyed by the penetration of spikes of reaction products. ,Also.

In order to solve the same problem caused by the reaction between the semiconductor substrate and the barrier layer provided at the junction between the shallow impurity region and the wiring in the semiconductor substrate, a metal layer deposited on top of the impurity and comprising a refractory metal or a transition metal that is active toward oxygen and forms a compound with the semiconductor substrate; The structure of the semiconductor device is configured to include a semiconductor layer that forms a compound with the semiconductor layer, and a wiring layer connected to the semiconductor layer, or an impurity region defined on one surface of the semiconductor substrate is exposed. An insulating layer provided with an opening is formed on the surface of the semiconductor substrate, and a metal layer made of a high melting point metal or a transition metal that is active in oxygen and that forms a compound with the semiconductor substrate is formed on the surface of the semiconductor substrate on which the insulating layer is formed. A semiconductor layer that forms a compound with the metal layer is formed on the metal layer, and the metal layer, the semiconductor substrate, and the semiconductor layer are reacted to generate a compound layer, and the surface of the semiconductor substrate is naturally oxidized. A method for manufacturing a semiconductor device is configured to include a heat treatment step for removing a film, and various steps of forming a wiring layer connected to the semiconductor layer after the heat treatment step.

[Industrial application field]

The present invention relates to semiconductor devices, and particularly to high-density, high-performance semiconductor integrated circuits that require minute impurity regions.

[Prior Art] For example, the source and drain regions of a MOS I-transistor are generally formed by ion-implanting impurities into a semiconductor substrate using a gate electrode as a mask. This method has the advantage that the source/drain regions can be formed in a self-aligned manner, but there is a limit in making the source/drain regions shallow. For example, the minimum possible depth of a p-type source/drain region containing boron (B) as an impurity is about 300 nm. This is because the lateral extent of impurity regions such as source and drain regions is affected by their depth. Therefore, the above-described ion implantation method is required for high-density semiconductor integrated circuits of 5, for example, 64 megapixels.

A fine impurity region with a lateral extent of about 1100 nm cannot be formed.

[Problems to be Solved by the Invention] Instead of ion implantation, a method has been proposed in which a shallow impurity region is formed by solid phase diffusion using a polycrystalline silicon layer doped with impurities as a diffusion source.

Solid phase diffusion methods are already used for the formation of emitter regions in bipolar transistors.

By the way, a natural oxide film of several nanometers exists on the surface of a semiconductor substrate such as silicon. This natural oxide film prevents impurity diffusion from the polycrystalline silicon layer to the impurity region in the solid-phase diffusion described above. Therefore, it is necessary to remove in advance the natural oxide film existing between the polycrystalline silicon layer serving as a diffusion source and the substrate. One method for removing the natural oxide film for this purpose is to heat-treat the semiconductor substrate at a high temperature of 1000°C or higher in an inert nuclear atmosphere before depositing polycrystalline silicon, which will serve as a solid phase diffusion source. . However, this method results in redistribution of impurities that have already been introduced into the semiconductor substrate.

There is a problem that the impurity region becomes deep.

On the other hand, when wiring made of aluminum or the like is connected to a silicon substrate, a titanium film, for example, is provided at the interface between the silicon substrate and the aluminum wiring layer in order to prevent mutual diffusion between the silicon substrate and the aluminum wiring layer. This titanium film functions as a barrier layer against the above-mentioned interdiffusion. A method has been proposed in which this titanium film is used to remove a natural oxide film on the surface of a silicon substrate. That is, the titanium film formed at the junction between the silicon substrate and the aluminum wiring as described above is subjected to heat treatment at about 600° C. to liberate oxygen on the surface of the silicon substrate. This oxygen.

It segregates in the silicide layer produced by the above heat treatment.

In this way, the native oxide film is removed at a low temperature that does not cause redistribution of impurities in the silicon substrate, and ohmic contact between the silicon substrate and the aluminum wiring is achieved.

However, in the heat treatment described above, titanium atoms diffuse into the silicon substrate at the same time as the silicon atoms of the substrate diffuse into the titanium layer. therefore.

Shallow impurity regions formed on the silicon substrate disappear, or titanium silicide protrusions (spikes)
There are problems such as the shallow impurity region being destroyed due to the penetration.

The present invention utilizes the natural oxide film removal effect of a barrier layer such as a titanium film to make it possible to remove a natural oxide film that is an obstacle to solid-phase diffusion, and also to remove shallow impurity films in the connection between a silicon substrate and aluminum wiring. It is an object of the present invention to provide a method capable of solving the above-mentioned conventional problem in which regions are destroyed by spikes of titanium silicide.

[Means to solve the problem]

The object is to provide a semiconductor substrate and a layer deposited on an impurity region defined on one surface of the semiconductor substrate of a refractory metal or a transition metal that is active toward oxygen and forms a compound with the semiconductor substrate. A semiconductor device according to the present invention, comprising a metal layer made of metal, a semiconductor layer deposited on the metal layer and forming a compound with the metal layer, and a wiring layer connected to the semiconductor layer. Alternatively, a step of forming an insulating layer provided with an opening exposing an impurity region defined on one surface of the semiconductor substrate, and a step of forming an oxygen-active material on the surface of the semiconductor substrate on which the insulating layer is formed. a step of forming a metal layer made of a high melting point metal or a transition metal and forming a compound with the semiconductor substrate; a step of forming a semiconductor layer on the metal layer that forms a compound with the metal layer; A heat treatment step for reacting the semiconductor substrate and the semiconductor layer to generate a compound layer and removing a natural oxide film on the surface of the semiconductor substrate, and forming a wiring layer connected to the semiconductor layer after the heat treatment step. This is achieved by the method of manufacturing a semiconductor device according to the present invention, characterized in that it includes the steps of: or the semiconductor device or method of manufacturing the same, wherein the semiconductor layer is an impurity diffusion source for the impurity region.

[For production]

For example, it has a structure in which a titanium film and a silicon layer are stacked on a silicon substrate. The titanium film is silicided by the low-temperature heat treatment, but at this time silicon is also supplied from the silicon layer on the titanium film, so the supply from the silicon substrate is suppressed.

Therefore, destruction due to disappearance of the shallow impurity region and silicide spikes is prevented. In the above heat treatment, the natural oxide film on the surface of the silicon substrate is removed. Moreover, a shallow impurity region can be formed by doping the silicon layer with an impurity after the heat treatment and diffusing the impurity into the silicon substrate.

As mentioned above, two aspects of the present invention are (1) conventional problems in wiring connection structures having a barrier layer made of a titanium film at the junction between a silicon substrate and an aluminum wiring, and (1) shallow impurity diffusion using, for example, a polycrystalline silicon layer as an impurity diffusion source. Both problems in the conventional method of forming regions can be solved.

Its scope of application extends to proprietary semiconductor devices featuring shallow impurity regions, such as high-speed MOS transistors, bipolar transistors, or thin film transistors.

〔Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a main part showing an example of a process when the present invention is applied to a MOS transistor.As shown in FIG.
The well-known LOGOS (Local Oxidation)
An isolation insulating layer 8 having a thickness of approximately 6,000 wafers is formed by the 5i-1icon method. Next, a gate electrode 9 made of, for example, polycrystalline silicon is formed in the element formation region exposed from the isolation insulating layer 8 according to a conventional method, as shown in FIG. 5B. The gate electrode 9 is insulated from the silicon substrate 1 by a gate insulating film 12, and its exposed surface is covered by a sidewall insulating film 13.

Next, a metal layer such as titanium (T) is applied to the surface of the silicon substrate 1.
i) A metal layer 6 of about 100 thick and of polycrystalline silicon and a semiconductor layer 4 of about 3000 thick are deposited one after another. Each of the metal layer 6 and the semiconductor layer 4 may be formed using a well-known method as appropriate.For example, a titanium layer may be formed by sputtering, and a polycrystalline silicon layer may be formed by CVD (chemical vapor deposition). The law can be used.

Next, using a well-known lithography technique, the semiconductor layer 4 and the metal layer 6 are patterned, as shown in FIG. These patternings.

The well-known RIE (reactive sputtering) using chlorine-based gas may be used.

Note that in the above, the metal layer 6 is made of tungsten (
k), a layer made of a high melting point metal such as molybdenum (MoL), tantalum (Ta), or a transition metal such as iron (Fe) or chromium (Cr) may be formed.The thickness of these layers is as follows:
The thickness is set such that the natural oxide film 7 existing on the surface of the silicon substrate 1 can be sufficiently removed by heat treatment to be described later. however,
Care must be taken not to excessively consume the surface of the silicon substrate 1 due to the silicidation reaction. For this reason, it is appropriate to have about 100 people.

Next, the silicon substrate 1 is subjected to a heat treatment (first heat treatment)' for 130 minutes at 450 DEG to 850 DEG C. in an inert atmosphere such as nitrogen. As a result, the metal layer 6.

1 by reacting with the silicon substrate 1 and the polycrystalline silicon layer 4
For example, titanium silicide (TiSiz) is produced. At the same time, oxygen on the surface of the silicon substrate 1 is liberated and segregated into the silicide layer. In this way, the natural oxide film 7 is removed.

After the above steps, the polycrystalline silicon layer 4 is doped with phosphorus (P) as an n-type impurity, for example, by ion implantation. At this time, phosphorus (P) is added to the isolation insulating layer 8 and the sidewall insulating film 13.
There is no problem even if it is injected. The ion implantation conditions are 1, for example, an ion acceleration voltage of 40 kV and a dose of 4.times.10@15 ions/cm".

Next, the silicon substrate 1 is subjected to a well-known PTA (Rapid Thermal Annealing Process) using, for example, infrared irradiation.
heat treatment at 900°C for seconds using the
2nd heat treatment).

As a result, phosphorus (P) doped into polycrystalline silicon N4
is diffused into the silicon substrate 1, and as shown in FIG.
An n-type shallow impurity region 2 is formed. In the same figure,
Reference numeral 3 is a silicide layer made of titanium layer 6.

Next, as shown in FIG. 2(e), an insulating layer 10 of approximately 1 μm thick made of, for example, PSG (phosphosilicate glass) is deposited on the metal surface of the silicon substrate 1, and polycrystalline silicon is deposited on this insulating layer 10. A contact hole with a diameter of about 1 μm exposing layer 4 is formed. The formation of this contact hole is 1
This may be performed by a well-known lithography technique and an RIE method using a fluorine-based gas. After that, a wiring layer 5 made of aluminum (AI), for example, is connected to the polycrystalline silicon layer 4.
is formed to complete the n-channel MO5) transistor according to the present invention.

Note that in the above, if the semiconductor layer 4 and the metal layer 6 are patterned as wiring extending on one isolation insulating layer 8, a multilayer wiring structure with these layers as the lower layer can be formed.

FIG. 2 shows 'the semiconductor layer 4 and the metal layer 6 in the above embodiment.
FIG. 3 is a cross-sectional view of a main part showing an example of a process in which these layers are formed by a self-line method instead of patterning.

In the same manner as in the above embodiment, 1, for example, a p-type silicon substrate 1 is prepared.
After forming an isolation insulating layer 8 and a gate electrode 9 on the surface, an insulating layer 10 made of, for example, SiO□ and having a thickness of about 1 μm is deposited over the entire surface of the silicon substrate 1, as shown in FIG. Then, to the insulating layer 10.

Openings 15 with a diameter of about 0.5 μm are formed to expose the source/drain regions. The opening 15 may be formed by a normal photolithography technique and an RIE method using a fluorine gas.

Next, 1 is applied to the surface of the silicon substrate 1 exposed in the opening 15.
For example, the metal layer 16 made of tungsten
Selectively grow to a thickness of 0 people. This selection is performed, for example, by a CVD method using a high melting point metal compound gas such as tungsten hexafluoride.

This allows the metal layer 16 to not be grown on the insulating layer 10.

Next, a semiconductor layer of approximately 3,000 layers thick, made of polycrystalline silicon, for example, is deposited over the entire surface of the silicon substrate 1.

This semiconductor layer also fills the opening 15 of the insulating layer 10. The semiconductor layer on the insulating layer 10 is etched back using a well-known method until the insulating layer 10 is exposed. the result,
As shown in FIGS. 3A and 3B, the semiconductor layer 14 is embedded in the opening 15. In this way, the metal layer 16 and the semiconductor layer 14 are formed in a self-aligned manner.

Next, the semiconductor layer 14 is heated to 600 to 500 ml in nitrogen gas, for example.
Heat treatment is performed at 850°C for 30 minutes (first heat treatment). As a result, the metal layer 6 reacts with the silicon substrate and the semiconductor layer 14 to produce, for example, tungsten silicide (WSiz). At the same time, oxygen on the surface of the silicon substrate 1 is liberated and segregates into the silicide layer. In this way, the natural oxide film 7 on the surface of the silicon substrate 1 is removed.

Next, the semiconductor layer 14 is doped with phosphorus (for example, phosphorus) as an n-type impurity.
P) is ion-implanted. The implantation conditions are 1, for example, an ion acceleration voltage of 40 kV, and a dose of 4 x 10'5 ions/
cm2. At this time, phosphorus (P) ions may be implanted into the insulating layer 10. After that, silicon substrate 1
1 is heat treated at 900° C. for 520 seconds (second heat treatment), for example, by the RTA method described above. By this heat treatment, the impurity doped in the semiconductor layer 14 is diffused into the silicon substrate 1, and an n-type shallow impurity region 2 is formed as shown in FIG. In addition, in the same figure, the reference numeral 3 indicates the metal layer 1.
This is a silicide layer consisting of 6.

After the above, a layer such as aluminum (A
A wiring layer 5 consisting of I) is formed to complete an n-channel MO transistor according to the present invention.

Even if the conductivity type of the silicon substrate 1 and the conductivity type of the impurities doped into the semiconductor layers 4 and 14 in each of the above-described embodiments are replaced, the present invention is still valid. Also, at least the surface is G
Even when using a substrate made of a compound semiconductor such as aAs, it is necessary to remove the native oxide film on the surface and to prevent the phenomenon that shallow impurity regions are destroyed by spikes made of reaction products with the wiring material semiconductor substrate. It is valid.

[Effects of the Invention] According to the present invention, a good ohmic contact is formed at the connection between a semiconductor substrate and a wiring, and a high-speed, high-speed semiconductor device consisting of a finely spaced S transistor bipolar transistor or a thin film transistor that requires a shallow impurity region It has the effect of improving the reliability and manufacturing yield of high-density integrated circuits, and promoting their practical use.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are process explanatory diagrams of an embodiment of the present invention. In fig. King is the silicon substrate, 2 is the impurity region. 3 is a silicide layer, 4 and 14 are semiconductor layers. 5 is a wiring layer, 6 and 16 are metal layers 7 are natural oxide films, and 8 is an isolation insulating layer. 9 is a gate electrode, and 10 is an insulating layer. 12 is a gate insulating film, and 13 is a sidewall insulating film. 15 is an opening. It is. Explanation diagram of the process of execution of the non-explosion day and month (Part 2) Fig.

Claims (5)

[Claims] (1) a semiconductor substrate; and a layer deposited on an impurity region defined on one surface of the semiconductor substrate, the layer being a refractory metal or transition metal that is active toward oxygen and forms a compound with the semiconductor substrate. A semiconductor device comprising: a metal layer made of metal; a semiconductor layer deposited on the metal layer and forming a compound with the metal layer; and a wiring layer connected to the semiconductor layer. (2) The semiconductor device according to claim 1, wherein the semiconductor layer is doped with an impurity introduced into the impurity region. (3) The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate is silicon. (4) forming an insulating layer on one surface of the semiconductor substrate with an opening exposing an impurity region defined on the surface; and forming an oxygen-active layer on the surface of the semiconductor substrate on which the insulating layer is formed. a step of forming a metal layer made of a high melting point metal or a transition metal and forming a compound with the semiconductor substrate; a step of forming a semiconductor layer on the metal layer that forms a compound with the metal layer; A heat treatment step for reacting the semiconductor substrate and the semiconductor layer to generate a compound layer and removing a natural oxide film on the surface of the semiconductor substrate, and forming a wiring layer connected to the semiconductor layer after the heat treatment step. A method for manufacturing a semiconductor device, comprising the steps of: (5) Following the heat treatment step for reacting the metal layer with the semiconductor substrate and the semiconductor layer, a step of implanting an impurity introduced into the impurity region into the semiconductor layer; 5. The method of manufacturing a semiconductor device according to claim 4, further comprising performing a second heat treatment step for diffusing the implanted impurity into the impurity region through the compound layer.