JPH0430471A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen a multilayered wiring in number of layers and a power wire and a ground wire in occupying area ratio by a method wherein a circuit element is provided to a semiconductor layer formed on the insulating layer deposited on a substrate, and the power wire or the ground wire formed of a high impurity concentration region is provided on the surface of the insulating layer. CONSTITUTION:A power supply wire 2 is formed of a high impurity concentration region formed on the whole chip by implanting impurity ions into a support substrate high in concentration. An insulating layer 3 of SiO2 is formed through thermal oxidation after the formation of the power supply wire 2. A multilayered wiring composed of a first wiring layer formed on a field insulating film 6 and a second wiring layer deposited on an interlaminar insulating film 9 is provided onto a semiconductor layer 4. The power supply wire 2 is connected to a circuit element 5 through a contact window 7 and a wiring 8. In a chip constituted as above, as the wiring layer 8 is provided to the first wiring layer, a wiring layer used for a power supply wire can be omitted from a multilayered wiring on a circuit element. Therefor, a multilayered wiring can be lessened in number of layers and ratio of the area occupied by a power supply wire and a ground wire to that of the multilayered wiring.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device equipped with a semiconductor chip that constitutes a circuit by providing a wiring layer on a circuit element, problems occur due to an increase in the number of layers when the wiring layer is multilayered. In order to alleviate the problem, the aim is to reduce the number of multilayer interconnections and the proportion occupied by power supply lines and ground lines. Further, the support substrate is configured to have a power line or ground line made of a high impurity concentration region on the surface of the insulating layer, and a chip having the above structure has a pad for the power line or ground line on the side surface thereof. The method for manufacturing the chip includes the steps of: forming the power supply line or the ground line separated by the scribe area in each chip area of the support substrate before being scribed into the chip;
forming a mark in a scribe area of the support substrate provided with the insulating layer; and forming the circuit element on the semiconductor layer on the insulating layer using the mark for alignment. Configure it as follows.

[Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to a semiconductor device including a semiconductor chip that forms a circuit by providing a wiring layer on a circuit element.

In the above-mentioned chips, as semiconductor devices become highly integrated, the wiring layers on the circuit elements become multilayered, and as the number of layers increases, various disadvantages occur, and therefore, it is desired to find a way to alleviate these disadvantages.

[Conventional technology]

A semiconductor device includes a semiconductor chip that constitutes a circuit, and the chip has a plurality of circuit elements arranged on the surface of a semiconductor substrate and connected by internal wiring to constitute a circuit. The internal wiring includes connection wiring between circuit elements, signal lines connecting the circuit elements to the outside, power supply lines, ground lines, and the like.

Conventional internal wiring is arranged in a wiring layer with an insulating film on the circuit element.

However, as semiconductor devices become more highly integrated, it becomes difficult to accommodate these internal wirings in a single wiring layer, and the internal wirings are arranged in multiple wiring layers.

Wiring arranged in multiple layers in this way is generally referred to as multilayer wiring, with the wiring layer provided on the insulating film on the circuit element serving as the first wiring layer, and the wiring layer placed over the insulating film on top of the first wiring layer. It is a stack of wiring layers in which a second wiring layer is provided, and recently there have been products with as many as 4 to 5 layers.

When the multilayer wiring has four or five layers, the upper one or two layers are occupied by the power supply line and the ground line. The reason why the power supply line and the ground line occupy a large area is because the wiring width becomes large due to the need to increase their current carrying capacity. Then, it is necessary to make the power line and ground line pads several times larger than the signal line pads.

(Problems to be Solved by the Invention) However, as the number of wiring layers increases in this way, the following disadvantages arise.

■Manufacturing yield decreases due to difficulty in manufacturing as the number of layers increases.

■Cranks occur in the insulation film between wiring layers due to increased heat generation in the wiring, making it easier to cause short-circuits between the eyebrows.

This heat generation is largely due to the power supply line and ground line through which large currents flow.

■If the power supply line or ground line covers almost the entire area of the chip, parasitic capacitance increases and failure analysis becomes inconvenient.

■When increasing the size of the power line or ground line pad, the pad area on the chip surface increases.

Therefore, the present invention provides a semiconductor device equipped with a semiconductor chip in which a wiring layer is provided on a circuit element to constitute a circuit, and when the wiring layer is multilayered, the number of layers and the proportion occupied by power supply lines and ground lines are as follows. The purpose is to reduce the

[Means to solve the problem]

In order to achieve the above object, a semiconductor device of the present invention has a circuit element in a semiconductor layer above an insulating layer on a semiconductor support substrate, and a high impurity concentration region on a surface of the support substrate on the insulating layer side. The chip having the above structure preferably has a pad for the power supply line or ground line on its side surface.

Further, the manufacturing method of the present invention for manufacturing the semiconductor device includes a step of forming the power supply line or the ground line separated by the scribe area in each chip area of the support substrate before being scribed into the chip; forming a mark in a scribe area of the support substrate provided with the insulating layer; and forming the circuit element on the semiconductor layer on the insulating layer using the mark for alignment. It is characterized by

In the manufacturing method, the mark is formed by providing a hole in the scribe area of the support substrate provided with the insulating layer before scribing, the width of which is narrower than the area, and the bottom of which exposes the support substrate; The film is filled with a 2N film that is the same as the insulating layer and the lower part is different, so that the mark portion is formed by reducing the thickness of the insulating layer, and when the alignment is performed, the difference in thickness is used. The hole may be recognized by the difference in color tone, or the hole may be filled with a film of a material having a lower etching rate than the insulating layer, and the semiconductor layer and the insulating layer may be locally etched away prior to forming the element. It is desirable to expose the top and side surfaces of the mark so that the mark can be recognized by the difference in level caused by the side surfaces during the alignment.

(Function) The chip of the semiconductor device described above is an SOI (Silico
A power supply line or a ground line is arranged under the insulating layer.

This power supply line or ground line can replace the power supply line or ground line conventionally placed in multilayer wiring on circuit elements, so the number of layers in the multilayer wiring and the proportion occupied by the power supply line or ground line can be reduced accordingly. So, the problem I mentioned earlier...
■Relieve. Moreover, since the insulating layer is interposed between the chip and the circuit elements, there is no adverse effect on the circuit constituted by the chip.

If the power line or ground line pad is provided on the side surface of the chip, the problem (2) can be alleviated.

In addition, in the manufacture of chips that make up circuits, generally a large semiconductor substrate from which multiple chips can be sampled from the front, back, left, and right is processed to form a circuit in each chip area at once, and a circuit is used to judge the quality of each chip area. A method is adopted in which a test (PP test) is performed, and then the chip regions are cut (scribe) to form individual chips.

When manufacturing the above chip according to this, the chip is S
In order to form an ol structure and have a power line or ground line under the insulating layer, the power line or ground line is formed on the support substrate before scribing, the above insulating layer is formed on it, and the circuit is formed on it. The procedure is to provide a semiconductor layer for element formation and then begin to form circuit elements and wiring layers thereon.

In that case, the above power supply line or ground line may be formed to communicate between chip areas, but in this case, when a defect occurs in some chip areas, other chip areas may be incorrectly determined as defective. This makes the PP test difficult.

In the manufacturing method of the present invention, it is possible to separate the power supply line and ground line formed on the support substrate in the scribe area.
This solves the above-mentioned difficulties of the P test.

However, since this separation defines the chip area before providing the semiconductor layer for forming the circuit elements, alignment is required when forming the circuit elements. In the manufacturing method of the present invention, the mark formed on the support substrate solves this alignment.

This alignment is performed in the exposure process for forming circuit elements, and since the alignment marks required by the exposure device exhibit differences in color tone or have steps, the manufacturing process of the present invention is advantageous. This is possible using either of the two marks shown in the method.

[Example] Examples of the semiconductor device and manufacturing method according to the present invention will be described below with reference to FIGS. 1 to 4.

1 and 2 are side sectional views schematically showing main parts of the first and second embodiments of the semiconductor device, FIGS. 3(a) to (e), and FIGS. 4(a) to (d). ) is a side sectional view of a main part for explaining the first and second embodiments of the manufacturing method, and the same reference numerals indicate the same objects throughout the drawings.

In FIG. 1, this figure schematically shows a part of the chip of the first embodiment of the semiconductor device, where l is a Si support substrate, 2 is a power supply line, 3 is an insulating layer of SOT structure, and 4 is for forming circuit elements. S of
i semiconductor layer, 5 a circuit element, 6 a field insulating film, 7
8 is the contact window for the circuit element, 8 is the wiring of the first wiring layer,
9 is an insulating film between the eyebrows, 10 is a contact window for the power line, 11
is the power line pad,

The power supply line 2 is formed by adding impurities to the supporting substrate 1 at a high concentration (10+9
/c+1 or more) This is a high impurity concentration region formed throughout the entire chip by ion implantation, and its thickness is 5 to 50 μm.
It is. The conductivity type is appropriately selected according to the configuration of the circuit element 5. The conductivity type of the support substrate 1 may be the same as the conductivity type of the power supply line 2 (or may be the opposite), since the power supply line 2 extends over the entire area of the chip in this case.

The insulating layer 3 is a SiO□ layer formed by thermal oxidation after the formation of the power supply line 2, and has a thickness of about 1 μm.

The thickness of the semiconductor layer 4 is about 3 μm when the circuit element 5 is a bipolar transistor, and about 0.1 to 0.5 μm when the circuit element 5 is a MOS transistor.

Above the semiconductor layer 4 is a multilayer wiring including a first wiring layer on the field insulating film 6, a second wiring layer (not shown) on the interlayer insulating film 9, and the like.

The power line 2 is connected to the circuit element 5 through a contact window 7 and a wiring 8. The contact window 7 extends from the field insulating film 6 through the semiconductor layer 4 and the insulating layer 3, and the semiconductor layer 4 is insulated by the insulating film on the wall surface.
(tungsten).

82 or poly-Si to provide electrical continuity between the power supply line 2 and the wiring 8. The insulating film on the wall surface was formed by depositing 5 iOz by CVD or spuntering, and by RIE leaving the side walls intact.

Further, the power line 2 is electrically connected to the power line pad 11 through a contact window 10 extending from the surface of the chip to the power line 2, and is connected to the outside from the band 11. This contact window 10
is similar to the contact window 7, but its cross section is much larger than the contact window 7 because it requires a large current carrying capacity. The pad 11 is also larger than a signal line pad (not shown).

In a chip having such a configuration, since the wiring 8 is arranged in the first wiring layer, the multilayer wiring on the circuit element 5 does not require a wiring layer for the power supply line. Therefore, this multilayer wiring reduces the number of layers and improves the chip manufacturing yield, significantly reduces heat generation, eliminates interlayer short circuits, and reduces parasitic capacitance.

However, since the power supply line pad 11 is arranged on the surface of the chip, the above-mentioned problem (2) remains as is.

Note that it is clear from the above description that the same effect can be achieved even if the power supply line indicated by 2 is a ground line. Further, in the above embodiment, the power line 2 occupies the entire area of the chip, but if the layout permits, the area of the power line 2 may be divided, and one side may be used as a power line and the other as a ground line. .

Then, in the multilayer wiring on the circuit element 5, the wiring layers of the power supply line and the ground line are removed, which further reduces heat generation and facilitates failure analysis. However, in that case, the conductivity type of the support substrate 1 needs to be opposite to that of the power supply line or the ground line, and it is preferable to provide a separation region between the power supply line and the ground line.

Next, in FIG. 2, this figure shows a part of the chip of the second embodiment of the semiconductor device, 12 is a power line pad, 13 is a contact window for the power line, 14 is a test pad, 15 is a package, 16 is the power line electrode of the package.

The chip of this embodiment differs from the chip of the first embodiment described above in the external connection structure of the power supply line 2. That is, a power line pad 12 is arranged on the side surface of the chip so as to be connected to the end surface of the power line 2, and is used in place of the power line pad 11 of the first embodiment.
A test pad 14 electrically connected to the power supply line 2 is arranged through a contact window 13 instead of the contact window 10 of the embodiment. The power line pad 12 is made of an Au film, and is formed by sputtering, vapor deposition, or plating using a mask on the chip.

The test pad 14 is used for PP testing, and has the same size as a signal line pad (not shown) because the current flowing through it is small. Accordingly, the cross section of the contact window 13 is extremely small compared to the cross section of the contact window 10 of the first embodiment. As a result, on the surface of the chip, the large power line pad 1
1 has been changed to a small test pad 14, and the above-mentioned problem (2) has been alleviated.

In this chip, the pad 12 is pressure bonded to the Au power line electrode 16 provided on the inner wall of the package 15, and the power source 12 is connected to the outside.

Next, an example of the method for manufacturing the above chip will be described.

In FIG. 3 showing the first embodiment, first, referring to (a), a large Si support substrate 1a (support substrate before scribing) from which a plurality of support substrates 1 can be collected in front, rear, left and right directions.
The supporting substrate 1a is formed by applying a mask and implanting impurity ions into the supporting substrate 1a.
Power supply lines 2 separated by scribe regions 22 are formed in each region (chip region 21) that will become the supporting substrate 1. Thereafter, an insulating layer 3 of SiO□ is formed over the entire surface by thermal oxidation.

Next, referring to (b), by etching with a mask applied, the width of the scribe area 22 is etched at appropriate locations (for example, four locations dispersed on the support substrate 1a) of the scribe area 22.
A hole 23 is formed which is narrower than the hole 23 and whose bottom exposes the support substrate 1a.

Next, referring to (C), the hole 23 is filled with poly-Si by a well-known method to form a poly-Si film 24. It is desirable that the surface of the poly-Si film 240 is lower than the surface of the insulating N3 by about 0.1 μm.

Next, referring to (d), the poly-Si film 24 is formed by thermal oxidation.
A SiO2 film 25 having a thickness of about 0.2 μm is formed on top of the film.

The surface of the SiO□ film 25 is absolutely perfect! It almost matches the surface of ii3.

The SiO□ film 25 is integrated with the 5iOz insulating layer 3 to form a thin region with respect to the insulating layer 3 having a thickness of about 1 μm, and serves as a positioning mark 25 in exposure in a later step.

Next, referring to (e), a semiconductor layer 4 is formed on the insulating layer 3 including the SiO□ film 25, and a circuit element 5 is formed on the semiconductor layer 4 by a conventional method. The semiconductor layer 4 can be formed by bonding a Si substrate of a size matching the support substrate 1a to the insulating layer 3 and polishing it to a predetermined thickness, or by growing poly-Si on the insulating layer 3 and irradiating it with energy beams. This is performed by recrystallizing the poly-Si. Also, the circuit element 5
In the formation of the chip region 21 due to the formation of the power supply line 2,
Since the position of the circuit element 5 has already been defined, the mark 25 is used for alignment during the exposure process in which the position of the circuit element 5 is determined. Since the thickness of the semiconductor layer 4 is approximately 3 μm or less, the mark 25 can be recognized by the difference in color tone between the exposed resist film and the insulating layer 2.

After this, multilayer wiring and other parts are formed by a well-known method to obtain the state before scribing, a PP test is performed, and then the scribe area 22 is scribed to separate the individual chip areas 21.
Cut it out to complete the desired chip. In the PP test, the power supply line 2 is independent for each chip area 21, so even if some chip areas 21 are defective, the test is not hindered.

By the way, in the case where the exposure apparatus recognizes and aligns marks based on differences in level, it is difficult to apply the above embodiment. In that case, a second embodiment described below may be used.

In the second embodiment, first, the hole 23 is
Proceed until the formation of (see Figures 3(a) and (b)).

Below, in FIG. 4, with reference to (a), the hole 23 is filled with poly-Si by a well-known method.
The marks 26 of the poly-Si film are formed by filling in the marks 26. mark 2
It is desirable that the surface of the insulating layer 6 coincides with the surface of the insulating layer 3.

Next, referring to (b), the semiconductor layer 4 is formed on the insulating layer 3 including the mark 26. This formation is the same as in the first embodiment.

Next, referring to (C), the semiconductor layer 4 and the insulating layer 3 are locally etched away to expose the top and side surfaces of the marks 26. In this etching, the marks 26 can be exposed by using an etchant for Si until the insulating layer 3 is exposed, and then switching to an etchant for 5iO7. The mark 26 has a step formed on the side surface and becomes a desired mark.

Next, referring to (d), circuit elements 5 are formed on the semiconductor layer 4 in the same manner as in the first embodiment. Marks 26 are used for positioning in the exposure process in its formation.

After this, a desired chip is completed in the same manner as in the first embodiment.

In this second embodiment, the poly-Si film 24 remaining after the formation of the 5iO7 film 25 of the first embodiment may be used as the mark 26. In that case, the number of steps will increase, but it will be easier to know when to switch the etchant for exposing the mark 26.

Note that the materials and dimensions used in the above description are not limited to those in the embodiments, and can be changed as appropriate depending on the target semiconductor device.

As understood from the above description, the present invention can be applied regardless of the number of wiring layers provided on a circuit element, and is particularly effective for highly integrated semiconductor devices. .

[Effects of the Invention] As explained above, according to the present invention, in a semiconductor device including a semiconductor nap that forms a circuit by providing a wiring layer on a circuit element, when the wiring layer is multilayered, By reducing the number of layers and the proportion occupied by power supply lines and ground lines, it is possible to reduce the problems caused by increasing the number of wiring layers, such as: - Decreased manufacturing yield, - Short-circuits between wiring layers, and - Increased parasitic capacitance of wiring. This has the effect of alleviating problems such as the inconvenience of failure analysis and the increase in the bad area on the surface of the chin 1.

[Brief explanation of drawings]

FIG. 1 is a side sectional view schematically showing a main part of a semiconductor device according to a first embodiment, FIG. 2 is a side sectional view schematically showing a main part of a semiconductor device according to a second embodiment, and FIG. 3(a) -(e) are side sectional views of main parts for explaining the first embodiment of the manufacturing method, FIGS. 4(a) to (d) are side sectional views of main parts for explaining the second embodiment of the manufacturing method, It is. In the figure, 1.1a is a Si support substrate, 2 is a power line, 3 is a 5iOz insulating layer, 4 is a Si semiconductor layer, 5 is a circuit element,
11.12 is a power line pad, 21 is a chip area, 2
2 is a scribe area, 23 is a hole, 24 is a poly-Si film, 25 is a mark of SiO□ film, and 26 is a poly-S film.
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Claims (1)

[Claims] 1) A circuit element is provided in a semiconductor layer on an insulating layer on a semiconductor support substrate, and a power supply line or a ground line consisting of a high impurity concentration region is provided on the surface of the support substrate on the insulating layer side. A semiconductor device comprising: 2) The semiconductor device according to claim 1, wherein the chip having the structure has a pad for the power supply line or the ground line on a side surface thereof. 3) forming the power supply line or the ground line separated by the scribe area in each chip area of the support substrate before being scribed into the chip, and marking the scribe area of the support substrate provided with the insulating layer. 3. The semiconductor device according to claim 1, further comprising: forming the circuit element on the semiconductor layer on the insulating layer using the mark for alignment. Production method. 4) The mark is formed by providing a hole in the scribe area of the support substrate on which the insulating layer is provided and before scribing, the width of which is narrower than the area and whose bottom exposes the support substrate, and the hole is formed so that the upper part of the hole is of the same material as the insulating layer. and the lower part is filled with two layers of different layers, and the mark portion is formed by making the thickness of the insulating layer thinner, and the difference in color tone due to the difference in thickness is formed during the alignment. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is recognized as follows. 5) The mark is formed by providing a hole in the scribe area of the support substrate on which the insulating layer is provided before scribing, the width of which is narrower than the area, and the bottom of which exposes the support substrate, and the hole has an etching rate higher than that of the insulating layer. prior to forming the element, the semiconductor layer and the insulating layer are locally etched away to expose the top and side surfaces of the mark; 4. The method of manufacturing a semiconductor device according to claim 3, wherein the recognition is made based on a step difference.