JPH0332230B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same;
In particular, it relates to the structure and formation method of wiring in semiconductor devices.

Hereinafter, a case will be explained in which a portion of the wiring having a two-layer structure according to the present invention, which is made only of a polycrystalline silicon (hereinafter simply referred to as Poly-Si) layer, is used as a fuse element, together with a conventional method for forming a fuse element.

Conventionally, in a semiconductor device represented by an IC memory in which a fuse element is formed on a semiconductor substrate along with a circuit function by a transistor element, the method for forming the fuse element is to use parts other than the fuse element, such as wiring materials for transistor circuits. When poly-Si is used as the fuse material, the fuse element and another poly-Si layer are formed in the same process, and then the fuse element and the circuitry surrounding the fuse element are connected to each other. Regardless of the material used or not, the fuse element is formed in an independent process, and then the fuse element and circuitry surrounding the fuse element are connected to each other.

For gate electrode material of N-channel MOS FET
Poly-Si is used, and the fuse material is Poly-Si.
The circuit operation, structure, and process of a conventional system will be explained using diagrams, using a transistor element and a fuse element using Si as examples.

Figure 1 shows a plan pattern diagram of an N-channel MOS FET and a fuse element. FIG. 2 shows a sectional view taken along line X-X' in FIG. 1, and FIG. 3 shows FIG. 1 as a circuit diagram.

In FIG. 1, a source diffusion layer 101 is connected to GND (ground) by an aluminum wiring 109 through a contact hole 105. One end of fuse element 104 is coupled to the V _DD power supply by aluminum wiring 111 through contact hole 108 . The other end of the fuse element 104 is connected to the aluminum wiring 11 through a contact hole 107.
0 and the aluminum wiring 110 is connected to the contact
It is coupled to the drain diffusion layer 102 by a hole 106. To change the state of the fuse element 104 from the connected state to the disconnected state, apply a high positive voltage to the Poly-Si gate electrode 103 to electrically conduct between the drain and source with very low resistance. A large current flows into the fuse element 104 from the V _DD power supply and blows it out. Further, a laser is directly applied to the fuse element 104 to blow it out. To detect the state of the fuse element 104,
By applying a normal operating voltage (for example, +5V) to the Poly-Si gate electrode 103, if it is in a coupled state, V _DD voltage will appear on the drain side aluminum wiring 110, and if it is in a disconnected state, the level of the drain side aluminum wiring 110 will be changed. is pulled to GND. The circuit operation has been explained above with reference to FIG.

Next, the structure and process will be explained with reference to FIG. A thick field silicon oxide film 216 is formed on the P-type silicon substrate 200 by a known method, and the transistor active region is selectively removed by etching. Furthermore, a silicon oxide film that will become the gate oxide film 203 is formed by thermal oxidation, and further becomes the gate electrode 204 and the fuse element 205.
Poly-Si is grown in a vapor phase to a thickness of about 5000Å. Then, the poly-Si other than the portion that will become the gate electrode 204 and the fuse element 205 is selectively removed by etching, and the silicon oxide film in the source ^and drain regions is also removed. A diffusion layer 202 is formed.

Next, a PSG insulating film 206,
A contact hole 210, 211, a drain region contact hole 209, and a source region contact hole 208 of the fuse element 205 are selectively removed by etching. Furthermore, thin Poly-Si of about 2000 Å
After vapor-phase growth, aluminum is selectively removed by etching after being vapor-deposited, and then the 2000 Å Poly-Si other than the aluminum portion is selectively etched to form aluminum wirings 212, 213, 21.
form 4.

Next, after forming a PSG film 215 by a vapor phase growth method, a fuse window 21 is formed on the upper part of the fuse element 205.
7 is selectively etched and completed.

The above is the structure and formation process of a fuse element using the conventional method.The fuse element formed using this method is formed in the same process as Poly-Si used for other circuits (gate electrodes in the figure). Therefore, it is usually thicker than 4000 Å.

However, as LSI technology progresses and the density of circuit elements increases, the unit area and power consumption per element become smaller, and the power required to blow a fuse element also becomes smaller. Therefore, the fuse element
By lowering the Poly-Si film thickness, it is possible to reduce the fusing power, but in the conventional method described above, if you try to make the Poly-Si even thinner, the wiring resistance of the Poly-Si used for the gate electrode, for example, will increase. This increases the load on the circuit that drives the gate electrode, causing problems such as slowing down the switching speed.

In addition, in order to eliminate the influence on components other than the fuse element, it is possible to form a thin fuse element through an independent formation process, but this increases the number of processes, which increases the cost and increases the number of causes of defects. become. By forming the fuse element thinly, even when the fuse element is fused by a laser, it can be blown with less laser energy, so damage to the surrounding area caused by the laser can be suppressed.

Furthermore, in order to improve the fusing characteristics of the fuse element, an opening is made in the protective film above the fuse element and used as a fuse window (fuse window 21 in Figure 2).
7) This is a well-known method, but in the conventional method of forming fuse elements, PSG is placed at the bottom of the fuse window.
Since no protective film is formed, the structure is such that the board is susceptible to external contamination from the fuse window.

In the present invention, a fuse element is formed by selectively placing a Poly-Si layer formed in the same pattern under metal wiring such as aluminum between the metal wiring, thereby eliminating the need to increase the number of process steps.
Achieves Si fuse and under Poly-Si fuse
By forming a PSG protective film, we took measures against external contamination from the fuse window.

According to the present invention, a
A MOS transistor and a polycrystalline silicon layer that is provided in a predetermined shape on the PSG film provided in the region where the MOS transistor is not formed and is thinner than the polycrystalline silicon that constitutes the gate electrode of the MOS transistor. , a metal layer formed on the polycrystalline silicon layer except for a predetermined portion, and a metal layer provided on the entire surface including the polycrystalline silicon layer and the metal layer,
and a protective insulating film provided with an opening that exposes only a part of the polycrystalline silicon layer in the predetermined portion without exposing the metal layer, and the predetermined portion of the polycrystalline silicon layer has a fuse element. Obtain the semiconductor device being formed.

Furthermore, according to the present invention, after forming a gate electrode made of a polycrystalline silicon layer via a gate insulating film on the main surface of the semiconductor substrate in a region where a MOS transistor is to be formed, a step of forming a source/drain region, and The process of forming a PSG film on the
A process of forming an opening in the PSG film above the drain region, a process of sequentially laminating a polycrystalline silicon layer thinner than the polycrystalline silicon layer of the gate electrode and a metal layer on the PSG film, and a process of sequentially laminating the metal layer and the polycrystalline silicon layer on the PSG film. A crystalline silicon layer is patterned into a predetermined shape, and a predetermined wiring made of the metal layer and the polycrystalline silicon layer is formed;
A process in which the metal layer is removed to form a predetermined fuse element portion consisting only of a polycrystalline silicon layer, and a protective film is formed over the entire surface, and a window is formed in the protective film to expose only the polycrystalline silicon layer of the fuse element part. A method for manufacturing a semiconductor device including a step of forming a hole is obtained.

A method for implementing the present invention will be described below using figures. FIG. 4 shows a plan view of a fuse element and an N-channel MOS FET according to an embodiment of the present invention. In FIG. 4, the structure is similar to that of the conventional system except for the fuse element section.
FIG. 5 shows a sectional view taken along YY' in FIG. 4. In FIG. 4, the portion 40 of Poly-Si 404 shown by the dotted line below the aluminum wiring 403, 405
6 shows a fuse element according to the invention. In addition, 40
1 is a drain diffusion layer, 402 is a contact hole, and 407 is an aluminum wiring forming a GND line. In FIG. 5, the steps up to forming the source/drain diffusion layer of the FET are as follows:
This is the same as No. 01 except that the Poly-Si fuse element is not formed in the same process. After forming the source/drain diffusion layer, PSG insulating films 502 and 511 are formed by vapor phase epitaxy, and source region contact holes 5 are formed by etching.
03 and drain region contact hole 50
4 is selectively removed.

Next, a thin poly-Si 508 of about 2000 Å is grown in a vapor phase, and then aluminum is vapor-deposited, and the aluminum is selectively removed by etching.
6,507 is formed. Furthermore, the Poly-Si5
08 is selectively removed by etching so that the area under the aluminum wiring and the fuse element remains.

Next, after forming a PSG film 509 by vapor phase growth, a fuse window 510 is formed above the fuse element to complete the process. In addition, 501 is Poly-Si forming the gate electrode, 502 is a PSG film, 503, 50
4 is a contact hole, and 511 is a PSG film.

As mentioned above, the Poly-Si under the aluminum wiring, which is used for the purpose of suppressing the reaction with the diffusion region of the aluminum wiring, is approximately 2000 Å thin and is directly connected to the aluminum wiring. For,
Suitable for fuse elements and eliminates the need for contact parts for connection.

Further, since the wiring forming process is performed after forming the PSG insulating film, in the fuse element formation according to the present invention, the PSG insulating film (the insulating film 51 in FIG.
1) is necessarily formed directly under the fuse element, and measures against external contamination can be taken without increasing the number of steps.

Using a fuse element as an example, we have explained the characteristics and formation method of wiring formed from a two-layer structure of a Poly-Si layer and a metal layer, which has a portion consisting only of a Poly-Si layer. It is also possible to use a portion consisting only of the -Si layer as a mere resistance element.

[Brief explanation of drawings]

Figure 1 is a plane pattern diagram of a conventional fuse element and N-channel MOS FET, Figure 2 is a cross-sectional view taken along line X-X' in Figure 1, and Figure 3 is a cross-sectional view of
3 is a symbolic circuit diagram of FIG. 2; FIG. 1 and 2, 200 is a P-type silicon substrate, 101 and 201 are source diffusion layers, and 10
2, 202 is a drain diffusion layer, 203 is a silicon oxide film forming a gate oxide film, 103, 204
is a Poly-Si layer forming a gate electrode, 104,
205 is a Poly-Si layer forming a fuse element;
206 and 207 are PSG films forming an insulating film, 1
05, 106, 107, 108, 208, 20
9, 210, 211 are contact holes, 10
9,212 is the aluminum wiring that forms the GND line, 1
10, 213 are aluminum wirings connecting the fuse element and FET, 111, 214 are aluminum wirings forming a power supply line, 215 are PSG films forming a protective film, 112, 217 are fuse windows, 2
Reference numeral 16 indicates a field silicon oxide film. FIG. 4 is a plan pattern diagram of a fuse element and an N-channel MOS FET according to the present invention, and FIG. 5 is a sectional view taken along Y-Y' in FIG. 4. In FIGS. 4 and 5, 501 is Poly-Si that forms a gate electrode, 502 and 511 are PSG films that form an insulating film and a protective film, 401 is a drain diffusion layer, and 402, 503, and 504 are contact holes. , 403, 506 are fuse elements
Aluminum wiring connecting FET, 404,50
8 is Poly-Si forming the fuse element, 4
05, 507 is the aluminum wiring that forms the power supply line, and 406 is the poly that forms the fuse element.
-Si fuse function section, 407, 505 are GND
Reference numeral 509 indicates an aluminum wiring forming a line, a PSG film forming a protective film, and 510 a fuse window.

Claims (1)

[Scope of Claims] 1. A MOS transistor provided on a semiconductor substrate, and a gate of the MOS transistor provided in a predetermined shape on a PSG film provided in a region where the MOS transistor is not formed. A polycrystalline silicon layer thinner than the polycrystalline silicon constituting the electrode, a metal layer formed on the polycrystalline silicon layer except for a predetermined portion, and a metal layer provided on the entire surface including the polycrystalline silicon layer and the metal layer. and a protective insulating film provided with an opening that exposes only a portion of the polycrystalline silicon layer in the predetermined portion without exposing the metal layer, wherein the predetermined portion of the polycrystalline silicon layer is A semiconductor device characterized by forming a fuse element. 2. After forming a gate electrode made of a polycrystalline silicon layer via a gate insulating film on the main surface of the semiconductor substrate in the formation region of the MOS transistor, a step of forming source/drain regions and a step of forming the entire surface.
a step of forming a PSG film, a step of forming an opening in the PSG film on the source/drain region, and a step of forming a polycrystalline silicon layer thinner than the polycrystalline silicon layer of the gate electrode on the PSG film and a metal the metal layer and the polycrystalline silicon layer are patterned into a predetermined shape, the metal layer is removed, and the polycrystalline silicon layer is removed. a step of forming a predetermined fuse element portion consisting only of a crystalline silicon layer; and a step of forming a protective film over the entire surface and opening a window in the protective film to expose only the polycrystalline silicon layer of the fuse element portion. A method for manufacturing a semiconductor device, comprising the steps of: