JPH0430600B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention performs processing such as DPCM (differential pulse coding modulation) encoding on an acoustic signal such as a musical tone signal,
The present invention relates to a time axis conversion device using encoded acoustic signal processing that changes the pitch of a musical tone or voice by compressing or expanding the time axis of the signal and outputting an acoustic signal.

[Background technology and its problems] As an audio device that processes musical tone signals and audio signals, the input audio signal (original sound) is converted into a digital signal by DPCM encoding, etc., and this digital audio signal is divided into blocks. Then, when reading these signals, the time axis of each block is compressed or expanded, and the blocks are read repeatedly or interleaved, so that the input acoustic signals can be reproduced almost in real time. Progress is being made in developing an audio signal time axis conversion device that uses coded audio signal processing to change the pitch without changing the length of the audio signal.

However, in this type of time axis converter, processing such as repeated reading and skipping due to signal compression and expansion must be performed using complex algorithms while checking the correlation of each signal block. The delay due to processing is large, and it is impossible to process and output such time axis conversion processing almost in real time while inputting the input signal,
Another problem was that the processing circuitry became extremely complicated.

Furthermore, if these algorithms are omitted and the device is simplified, there is a problem in that the sound quality, hearing sensation, etc. of the decoded audio signal (playback sound) deteriorates.

The present invention has been made to solve the above-mentioned problems, and is capable of performing time-base conversion processing for compressing or expanding an acoustic signal almost in real time, which changes the pitch without changing the length of the sound. It is an object of the present invention to provide an audio signal time axis conversion device using encoded audio signal processing that can obtain an output signal with good clarity and audibility with a relatively simple circuit configuration.

[Configuration] The configuration of the audio signal time axis conversion device according to the present invention is to input an analog audio signal, encode the analog audio signal into a digital signal, and mark the digital signal to indicate a cut point. The digital signal, which has been marked and divided into predetermined block lengths, is sequentially written into a read/write memory as encoded information, and the encoded signal in the memory is divided into predetermined block lengths. When reading out the digital signal for each block of information and decoding it into an analog audio signal, the time of the audio signal can be changed by changing the period of writing the digital signal into the memory and the period of reading it from the memory. In an acoustic signal time axis conversion device that performs axis conversion, when compressing the time axis, the address of the encoded information with the mark in the latest block already written in the memory is temporarily stored, and the time axis is compressed. address storage means for temporarily storing the address of the encoded information with the mark in the latest block currently written in the memory; When the mark is detected from each piece of read encoded information and the time axis is compressed based on the detection interval of the mark for each piece of encoded information, the interval between two detected marks at the time of writing is compressed. When two marks are detected during reading, it is synchronized with the second mark during reading, and when the time axis is extended, while two marks are detected during reading. a mark detection circuit that outputs a load signal in synchronization with the second mark during reading when two marks are detected during writing; and a mark detection circuit that outputs a load signal in synchronization with the second mark during reading; a read counter that sequentially advances the address and presets the address temporarily stored in the address storage means as the start address of the block for the next read when receiving the load signal from the mark detection circuit; The digital signal is read from the memory based on the address of the read counter.

[Operations and Effects of the Invention] The audio signal time axis conversion device according to the present invention having the above-described configuration inputs an analog audio signal, encodes the analog audio signal into a digital signal, and divides the analog audio signal into a digital signal. The digital signal is divided into predetermined block lengths by adding marks representing points, and the digital signals that have been marked and divided into predetermined block lengths are sequentially written as encoded information into a readable/writable memory. When reading a digital signal block by block from encoded information and decoding it into an analog audio signal, the time axis conversion of the audio signal is performed by changing the period at which the digital signal is written to the memory and the period at which it is read from the memory. I'm going.

When compressing the time axis, the address storage means temporarily stores the address of encoded information with a mark in the latest block already written in the memory, and the mark detection circuit A mark is detected from each of the coded information read from the memory and the coded information read from the memory, and based on the detection interval of the mark for each piece of coded information, the mark is detected at the time of reading while two marks are detected at the time of writing. When two marks are detected, in synchronization with the second mark at the time of reading,
Outputs load signal.

Upon receiving the load signal, the read counter transfers the marked coded information in the latest block that has already been written to the memory, which is temporarily stored in the address storage means, to the starting address of the block for the next read. Preset as .

In addition, in the case of time expansion, the address storage means temporarily stores the address of encoded information with a mark in the latest block currently written in the memory, and the mark detection circuit A mark is detected from each of the coded information to be written and the coded information read from the memory, and based on the detection interval of the mark for each piece of coded information, write is performed while two of the marks are detected at the time of reading. When two marks at the time are detected, in synchronization with the second mark at the time of reading,
Outputs load signal.

Upon receiving the load signal, the read counter transfers the address of the marked coded information in the latest block currently written to the memory, which is temporarily stored in the address storage means, to the next block for reading. preset as the start address of

Reading of the digital signal based on the address of the read counter is normally performed while sequentially advancing the address in accordance with the read cycle.

Therefore, when compressing or expanding the time axis, each block is compressed or expanded and read out according to the read cycle, so there is a risk that the read address will overtake the write address or that the read address will be significantly delayed from the write address. Occurs. The mark detection circuit determines the presence or absence of such a possibility based on the mark detection interval for each encoded information detected from the encoded information written to the memory and the encoded information read from the memory, and When it is determined that there is a risk of this, a load signal is output. Based on the load signal, the read counter presets the address temporarily stored in the address storage means as the leading address for the next read. At this time, the address temporarily stored in the address storage means is the address of the marked encoded information of the latest block already written in the memory in the case of time axis compression, and the address of the encoded information with the mark of the latest block already written in the memory in the case of time axis expansion. This is the address of the marked encoded information of the most recent block written to memory. Therefore, by presetting the read counter, in the case of time axis compression, the latest block that has already been written to the memory is repeatedly read out, and in the case of time axis expansion, the block immediately before the latest block currently being written is performed. Skipping is performed.

In the present invention, by performing such repeated reading or skipping, the reading side follows the writing side (while ensuring that the reading does not overtake the writing in the case of time axis compression), Most of the time axis conversion processing for compression or expansion of audio signals is performed in real time.

Moreover, according to the acoustic signal time axis converting device according to the present invention, the mark detection circuit determines whether it is necessary to repeatedly read or skip a block, and only when necessary, presets the read counter with a necessary address. Therefore, the minimum necessary processing can be quickly realized with a relatively simple circuit configuration, and an output signal with good clarity and audibility can be obtained.

Embodiments of the present invention will be described below based on the drawings.

Figure 1 shows a system that inputs an analog audio signal such as a musical tone or voice, performs DPCM encoding processing, and also performs time axis conversion that involves compression and expansion of the encoded signal without changing the length of the sound, that is, the playback speed. 1 is a block diagram of an audio signal time axis conversion device that subtly changes the pitch of the reproduced sound of the decoded audio signal. Reference numeral 2 designates an input filter that inputs and filters an analog audio signal such as a voice or a musical tone signal input from the input terminal 1, and sets a band by removing unnecessary frequency components and noise for audio signal processing. A compressor 3 compresses the amplitude of the input signal sent from the input filter 2, compressing the signal amplitude for noise reduction operation, and amplifying the signal in an expander of the decoding circuit described later. 4 is a sample for sampling the analog audio signal sent from the compressor 3.
This is a hold circuit, and instantaneous amplitude values of a continuous acoustic signal waveform are taken out as sample values according to the time intervals of sampling pulses sent from the write/read controller 8. Reference numeral 5 denotes an A/D converter that quantizes the signal sampled by the sample-and-hold circuit 4 and converts it into a binary code.
A differential encoding type A/D that quantizes and encodes the difference between α times the decoded value before the sample)
It is a converter. 6 is the encoded information (data) sent from the A/D converter 5,
This is a write latch that latches in order to sequentially store data in a register with a storage capacity for several blocks of acoustic signals provided in a read/write memory (RAM) 7. Data is latched by a latch signal supplied from a read/write controller 8. Temporary memory, RAM
When a write permission signal is sent from the multiplexer 7, which will be described later, the encoded data is sent to the RAM 7 through the data bus, and the encoded data is sequentially written into the designated addresses of the RAM 7.

9 indicates, for example, the least significant bit (LSB) when writing encoded data to RAM 7.
This is a marking circuit that adds a mark (for example, a code of logic "1") to designate a cutting point of a block read from the RAM 7 when performing time axis conversion by compression/expansion of a signal. This marking circuit 9 includes a peak detection section that inputs the analog audio signal from the compressor 3, detects its peak, and outputs a peak detection signal, and an encoder that outputs the analog audio signal from the A/D converter 5 to the write latch 6. Check the information on the most significant bit (MSB) of the signal, that is, the sign of the encoded data, and at the same time as inputting the peak detection signal, when detecting the zero crossing point when the encoded data transitions from negative to positive, the pulse a zero-cross detection unit that outputs a marking command signal of the form; and a mark that indicates a block cutting point, for example, at the least significant bit (LSB) of the encoded data output from the A/D converter 5 in response to the marking command signal. (for example, a code of logic "1") is provided.

Reference numeral 10 denotes a timer circuit that masks the peak detection signal output from the peak detection section of the marking circuit 9 for a preset period of time and stops outputting the signal. A high-level masking signal is output to the peak detection section for a predetermined masking time from the rising edge. Note that the timer circuit 10 is equipped with a second timer section that operates when a silent input signal is input. In order to avoid cases in which the marking is not performed over and over, if the marking command signal is not output from the zero-cross detection section of the marking circuit 9 even after the time set in the second timer section has elapsed, the marking of the marking circuit 9 is forcibly executed. The marking command signal is configured to output a marking command signal to the section.

In this way, when performing time axis conversion, RAM7
The length of the block read from the block is determined approximately by the time interval between the marks indicating the cutting points, that is, by the set time of the timer circuit 10.

Reference numeral 11 is a control circuit, and if the length of the block at the time of writing is constant, when time axis conversion is performed with the length of the reproduced sound being constant, the readout will depend on the degree of compression or expansion of the signal. The number of cutting points for each block of the input signal changes greatly, but in order to reduce the change in the number of cutting points, the length of the block at the time of writing is changed by changing the setting time of the timer circuit 10. The control necessary for encoding and decoding is performed.

Reference numeral 12 is a pitch setting device for setting the pitch ratio between the original sound and the reproduced sound in order to change the pitch of the reproduced sound higher or lower with respect to the input sound, and its operation adjusts the reading speed of encoded data from the RAM 7. The pitch can be changed without changing the length of the original sound. This pitch setting device 12 is a read counter 1.
The variable clock signal generator 1 changes the period of the read clock signal i applied to the clock signals 4a and 14b.
It is configured as a variable resistor provided at 3.

14a and 14b are read counters for specifying the address when reading encoded data from the RAM 7, and are constructed of presettable counters, and are blocks for reading the address latched by latch C19 and latch D20, which will be described later. The first address is preset by the load signals j ₁ and j ₂ from the mark detection circuit 21, and the count is advanced from that address by the clock signal i applied from the variable clock signal generator 13. The encoded information specified in is sent to RAM7.

15 is a clock signal generator that outputs a clock signal to the write/read controller 8 and the write counter 16;
A divided write clock signal h for addressing RAM 7 is sent. On the other hand, in the write/read controller 8, the clock signal generator 15
Sample pulse signal a, A/D conversion reference clock signal b for A/D converter 5, write latch signal c, RAM
7, a memory write enable signal d, a memory read enable signal e, read latch signals f ₁ , f ₂ , and
A selection pulse signal g is generated to be sent to the multiplexer 17 for switching between write and read operations of the RAM 7. and encoded data RAM
The timing of writing to and reading from data 7 is controlled so as to be performed continuously, for example, during one period of the write clock signal h. The write counter 16 is a ring counter that indicates a value corresponding to the address of the encoded data area in the RAM 7, and counts by inputting the clock signal h, and sends the write address to the RAM via the multiplexer 17.
Send to 7. Therefore, when writing encoded data to the RAM 7, the encoded data is first temporarily stored in the write latch 6 by the write latch signal C sent from the write/read controller 8 to the write latch 6, and then set on the data bus. , RAM7
While the multiplexer 17 is switched to the write side by making the write enable signal d active, encoded data is sequentially written to the addresses specified by the write counter 16.

18 is a latch C1 as an address storage means.
9 and latch D20, and is composed of a circuit equipped with a D-type flip-flop and a gate as shown in FIG. The synchronized latch enable signals o, q and strobe signals r, p are sent to the latch C19 and the latch D20, and the latch C19 and the latch D20 alternately read the address sent from the write counter 16 at the timing of the block separation point indicated by the marking signal Ma. Memorize information temporarily.

21 is a mark detection circuit, which detects the mark signal m at the block division point added to the encoded data sequentially written in the RAM 7, and also detects the mark signal m at the block division point.
As shown in the timing chart of FIG. 7 and FIG. 7, when reading the encoded data, marks in the encoded data are detected according to the reading speed and a mark detection signal De is output, and two consecutive mark signals m are detected. When two mark detection signals De are generated in between, or when two mark signals m are generated between two consecutive mark detection signals De, a load signal n is generated in synchronization with the second mark detection signal De. occurs. This load signal n is divided into every other load signal j ₁ and load signal j ₂ , and each is sent to two read counters A14 through an OR gate.
a, is sent to the read counter B14b, and the read counters A and B use the load signals j ₁ and j ₂ to preset the address data that will be the start of reading by the latch C19 or the latch D20.
The reason why such two reading counters A and B are used to read the encoded data in two systems is to prevent skipping or repeated reading of the encoded data at the signal block division point. This is to eliminate noise caused by deviations in waveforms due to differences in signal pitch and amplitude, and the mutually inverted envelope signals EnA and EnB output from the envelope circuits 22a and 22b are output from the readout latch A23a and the readout latch B23b. applied to the reference inputs of two D/A converters 24a and 24b to which encoded data is input, respectively;
Each block is not connected immediately; instead, when the previous data block passes the cut point, its output is gradually throttled down, and the new data block gradually increases its output from the cut point, so that Signal connections are being made.

The above-mentioned 23a and 23b are two readout latches, respectively, and the readout latch signal f ₁ or f ₂ from the write/read controller 8 is sequentially inputted to the multiplexer 17 in synchronization with the readout selection of the selection pulse signal g. When switched to the read side, the read counter A14
addressed by a or B14b;
The encoded data read from RAM 7 onto the data bus is latched.

24a, 24b are readout latches A23a, B2
3b is a D/A converter that inputs the coded signal latched and converts it into an analog signal,
The signals output from the D/A converters 24a and 24b are sent to an integrator 25 for integration, and then sent to an expander 26 to restore the signal amplitude compressed by the compressor 3 at the time of input, and then output. The signal is sent to a filter 27, and is configured so that an analog audio signal whose time axis has been converted and whose pitch has been changed can be obtained from an output terminal 28.

Although not shown in the block diagram of Figure 1, it is not only possible to input an original sound such as a musical tone signal and simply change the pitch by time axis conversion processing and output it, but also to provide a mixer circuit on the output side to convert the original sound signal. By mixing and outputting a time-axis converted reproduced sound signal with a specific pitch ratio that forms a consonant interval with respect to the original sound, for example, a consonant tone with a harmonic third or fifth degree can be produced from a single sound source. can also be generated.

Next, the operation of the time axis conversion device will be explained with reference to the waveform diagrams and timing charts of FIGS. 3 to 8.

First, the pitch setting device 12 sets the pitch ratio (interval ratio) between the input original sound and the output reproduced sound. For example, when the pitch ratio is set to 1:2, it means that the frequency of the reproduced sound is converted to twice that of the original sound.For example, if the input musical sound signal is the sound of "C", the reproduced sound is the sound of "C" which is an octave higher. By setting this pitch ratio, the variable clock signal generator 13
The period of the clock signal is adjusted in inverse proportion to the pitch ratio based on the period of the fixed clock signal of the clock signal generator 15 sent to the writing side circuit, and the read speed is adjusted based on the signal writing speed. It will increase in proportion to the ratio.

An acoustic signal such as a musical tone signal is input from an input terminal 1, and passes through an input filter 2 to remove frequency components and noise unnecessary for signal processing from the signal.
Sent to compressor 3. The compressor 3 compresses the amplitude of the audio signal for noise reduction, etc. The amplitude-compressed analog audio signal is sent to the DPCM encoding processing circuit, and first input to the sample/hold circuit 4 where sampling is performed. It will be done. Sampling is performed at the time interval of the sampling pulse signal a sent from the write/read controller 8, and each amplitude value is held as a sample value. The signals sampled by the sample-and-hold circuit 4 are then sent to the A/D converter 5, where the differences between these signals are quantized and converted into binary codes. That is, here, the difference between the continuously inputted and sampled signal and the predicted signal is taken and quantized, and the quantized signal data is encoded into a binary number. With A/D converter 5
The encoded data of the acoustic signal that became the DPCM code is
It is then sent to write latch 6 and latched by latch signal C supplied from write/read controller 8. The encoded data latched by the write latch 6 is sequentially sent to the RAM 7 and transferred from the write counter 16 to the multiplexer 17.
The data is written into the RAM 7 in synchronization with the encoding cycle while being addressed based on the address signal supplied through the RAM 7.

On the other hand, when the encoded data is sent from the A/D converter 5 to the write latch 6 and temporarily stored, the control circuit 11 adds a mark indicating the block division point of the signal to the least significant bit of the encoded data. The sound signal is applied at intervals based on the set time of the timer circuit 10, and at the peak position of the acoustic signal as follows.

That is, the analog audio signal S output from the compressor 3 is input to the peak detection section of the marking circuit 9 to detect the peak of that page, and at this time, the timer circuit 10 outputs the previous signal as shown in FIG. After the marking signal is output, an output signal v that masks the peak detection signal t for a set time T _n is output to the peak detection section, and peak detection during this period is canceled. Therefore, the interval between the marks indicating the cutting point, that is, the length of the block, is determined to be approximately constant by the set time of the timer circuit 10 controlled by the control circuit 11. Such a peak detection signal t is sent to the zero-cross detection section, and at the same time as the peak signal is input, each bit is When a zero-crossing point where the positive/negative signal of the data changes from negative to positive is detected, a marking command signal u is generated in the marking circuit 9, and a block cutting point is set, for example, at the least significant bit of the encoded data latched in the write latch 6. A mark indicating, for example, a logic "1" is attached.

Note that if the silent signal continues, the peak of the acoustic signal cannot be detected and marking cannot be performed; however, in such a case, the second timer section in the timer circuit 10 detects the mask signal v
After the set delay time from the falling edge of the block, the output signal is output to the zero-cross detection section, and a marking command signal is generated unconditionally.As above, the mark indicating the block cutting point is part of the encoded data. granted to. Of course, the set delay time of the second timer section is also controlled by the control circuit 11 in the same way as the mask time of the timer circuit 10.

On the other hand, the encoded data stored in the RAM 7 is transferred to the pitch setter 12 by the operation of the reading side circuit.
The signal is read out from the RAM 7 almost in real time as follows at a readout speed based on the pitch ratio set in , and while compressing or expanding the signal.

First, a case in which the pitch of reproduced sound is increased by compressing the time axis and repeating readout will be explained with reference to FIG. The graph in Figure 6 shows the change over time in the address of each counter for writing and reading, where the solid line A shows the change in address during writing, and the dashed line B shows the change in address during reading. , points a to f in the figure are marks of block division points during writing. The mark detection circuit 21 receives a mark signal m indicating a mark attached to encoded data during writing, and when reading,
A mark detection signal De is generated which becomes active when the address of the read counters A14a and B14b reaches the mark address (points a to f) indicating the block division point. Then, the mark signal m during writing and the mark detection signal De during reading
When two mark detection signals De are generated between two consecutive mark signals m, the mark detection circuit 2 is activated in synchronization with the second mark detection signal De.
1, a load signal n is generated. and,
Every other load signal n is divided into a load signal j ₁ and a load signal j ₂ , which are sent to two read counters A14a and two read counters B14b via an OR gate, respectively.
14b is connected to latch C by these load signals _j1 and _j2.
19 and D20, the address data that is latched at the beginning of the readout is preset, and the count is advanced by the clock signal i according to that address.
When the multiplexer 17 is switched to the read side by the selection pulse signal g sent from the write/read controller 8 to the multiplexer 17, the read enable signal e to the RAM 7 is activated, and the read counter A14a or B
Encoded data is sequentially read out from the address specified by 14b.

In this way, the solid line A indicates the data writing speed.
When the slope of the dashed-dotted line B indicating the readout speed is large with respect to the slope of By repeatedly reading the previous block to prevent the read data address from overtaking the write data address, and by repeatedly reading the minimum necessary number of blocks during time axis compression, the signal block can be The number of connection points is reduced and the hearing sensation is improved.

The encoded data read from the RAM 7 and set up on the data bus is alternately latched by the read latch A 23a and the read latch B 23b by the read latch signals f ₁ and f ₂ output from the write/read controller 8. , are sent to two D/A converters 24a and 24b. D/
The A converters 24a and 24b convert the differentially encoded signal into an analog signal, and the encoded data block output from each D/A converter 24a and 24b is converted by the envelope signals EnA and EnB applied to the reference inputs. The amplitude is adjusted so that the pitch of the analog signal waveform at the beginning and end of the signal has a smooth slope, that is, the envelope of the signal goes from small to large at the beginning and from large to small at the end. . Then, the two output signals are combined and sent to an integrator 25 to be decoded into a complete analog signal, and then returned to the original signal amplitude by an expander 26, passed through an output filter 27, and is output from an output terminal 28. An acoustic signal whose pitch has been raised by signal compression processing of time axis conversion is output.

On the other hand, when extending the time axis to lower the pitch of the reproduced sound, reading is performed by skipping blocks as shown in the graph of FIG. That is, the graph in FIG. 7 shows the change over time in the address of each write and read counter, as in FIG. In the figure, points a to f are marks of block division points during writing. The mark detection circuit 21 receives a mark signal m indicating a mark attached to encoded data during writing, and when reading,
When the addresses of the read counters A14a and B14b reach the address (points a to f) of the mark indicating this block division point, a mark detection signal De which becomes active is generated. Then, the mark signal m during writing is compared with the mark detection signal during reading, and when two mark signals m are generated between two consecutive mark detection signals De, the second mark detection signal De is detected. A load signal n is generated in the mark detection circuit 21 in synchronization. Then, as in the case of time axis compression described above, the load signal n is 1
The load signals j ₁ and j ₂ are divided every third and sent to two read counters A14a and B14b, respectively, and the read counters A14a and B14b are sent from the latches C19 and D20 by the load signals j ₁ and j _2. Preset the start address data for reading. In the case of time axis expansion processing, the marking signal Ma input to the readout controller 18 is input to the flip-flop without being inverted, and the latch enable signals o and q in FIG. 5 alternate at the rising edge of the marking signal Ma. . Therefore, the load signals j ₁ and j ₂ cause the read counters A14a,
The address preset in B14b is not the address of the previous data as in the case of compression processing, but the address of the latest block division point, which improves the ability to follow the original sound when reading. become. The preset read counters A14a and B14b advance the count from the address by the clock signal i, and when the multiplexer is switched to the read side by the selection pulse signal g sent from the write/read controller 8 to the multiplexer 17, the read counters A14a and B14b advance the count from the address to the RAM 7. The read enable signal e of the read counter A is activated, and the read enable signal e of the read counter A
Encoded data is read from the address specified by 14a and B14b. In this way,
If the time difference between read and write processing becomes large, skip one block and read the next block, extending the time axis without changing the length of the sound and lowering the pitch. Processing is performed. Then, similarly to the compression process described above, the read encoded data is transferred to the read latches A23a and B2.
3b alternately latches each series of blocks, and is decoded and synthesized by the decoding circuit.
It is output as an analog audio signal, and a playback sound with a lowered pitch is created.

In addition, as mentioned above, the integrator 25
The envelope of the signal sent to the D/A converter 24a is schematically represented in FIG.
The converter 24b outputs a signal as shown in parentheses, for example, and as a result, the input signal to the integrator 25 has a shape shown in parentheses.

Note that the acoustic signal of the reproduced sound whose pitch has been changed with respect to the original sound by the time axis conversion process is mixed with the original sound input signal by a mixing circuit provided on the output side (not shown), so that, for example, two sounds are mixed with each other. If there is a consonant relationship, it is possible to create a harmony of consonant intervals.

Furthermore, such a time axis conversion circuit does not perform time axis compression or expansion processing, and instead outputs sounds of the same length and pitch, that is, the original sound and the same reproduced sound slightly delayed from the original sound, through a mixing circuit. By doing so, reverberation can be added. The control circuit 11 adds reverberation through signal delay processing.
This is done by the action of That is, the control circuit 11, which has received the command signal for adding reverberation, sends delay data set by a delay value setting switch (not shown) to the read counters 14a, 14b via an OR gate group. And the control circuit 11
sends a reset signal to the write counter 16 to set the count to zero, and further applies a delay load signal to the read counters 14a and 14b via the OR gate. At this time, the mark detection circuit 21 and the latches 19 and 20 are inactive, and the output is at a low level. Through such processing, the read counters A14a and B14b advance counting from the preset delay data address using the same clock signal as the write counter 16.
Write counter 16 and read counter A14a,
Reverberation can be added by displacing B14b, performing signal output delay processing, and mixing this output acoustic signal with the original sound signal.

As explained above, according to the audio signal time axis conversion device of the present invention, when compressing or expanding the time axis of an audio signal, data written to the RAM is performed while performing repeated readout or skip processing associated with this. Since it is possible to decode the latest encoded information and perform time axis conversion processing almost in real time, it is possible to perform pitch conversion of musical tones and voices in real time to generate consonance with the original sound, It can be used for a wide range of purposes, such as generating special sounds. Furthermore, an output signal with good clarity and audibility can be obtained with a relatively simple circuit configuration.

[Brief explanation of drawings]

The figures show an embodiment of the present invention; Fig. 1 is a block diagram of the time axis conversion device, Fig. 2 is a circuit diagram of the readout controller, Fig. 3 is a waveform diagram of each signal that performs marking processing, and Fig. 4 is a block diagram of the time axis conversion device. Fig. 5 is a timing chart of each signal input/output from the write/read controller. Fig. 6 is a graph showing temporal changes in write/read addresses during time axis compression. and a timing chart of each signal, FIG. 7 is the same graph and the same timing chart when the time axis is expanded, and FIG. 8 is a waveform diagram schematically showing the envelope of the input waveform of the integrator. 5...A/D converter, 6...Write latch, 7
...RAM, 8...Write/read controller,
9... Marking circuit, 14a, 14b... Read counter, 16... Write counter, 17...
...Multiplexer, 18... Read controller, 19, 20... Latch, 21... Mark detection circuit.

Claims (1)

[Scope of Claims] 1. An analog audio signal is input, the analog audio signal is encoded into a digital signal, and the digital signal is divided into predetermined block lengths by adding a mark indicating a cutting point, and the digital signal is divided into predetermined block lengths, The digital signal divided into predetermined block lengths is sequentially written as encoded information into a readable/writable memory, and the digital signal is read out block by block from the encoded information in the memory to generate analog audio. In an acoustic signal time axis converting device that converts the time axis of an acoustic signal by changing the period of writing the digital signal to the memory and the period of reading it from the memory when decoding the signal, When compressing the axis, the address of the encoded information with the mark in the latest block already written to the memory is temporarily stored, and when expanding the time axis, the address of the coded information currently written to the memory is stored. address storage means for temporarily storing an address of encoded information to which the mark is attached in the latest block; and detecting the mark from each of the encoded information written to the memory and the encoded information read from the memory. , when compressing the time axis based on the detection interval of the mark for each piece of encoded information, when two marks are detected during writing and two marks during reading are detected. In synchronization with the second mark at the time of reading, and when extending the time axis, when two marks at the time of writing are detected while two marks at the time of reading are detected, the readout is performed. a mark detection circuit that outputs a load signal in synchronization with the second mark of the time; and a mark detection circuit that outputs a load signal in synchronization with the second mark of the time; a read counter that presets the address temporarily stored in the address storage means as the start address of a block for the next read when the read counter receives the digital signal from the memory based on the address of the read counter. An acoustic signal time axis conversion device characterized by reading out.