JPS60263375A - Time axis converter of acoustic signal - Google Patents

Abstract

PURPOSE:To obtain an acoustic signal having high clarity and high sudible properties through a simple circuit by storing an address of the coding information containing a mark together with an address preceding the first addressby a step and defining either one of the addresses stored in response to the address setting signals as a head address of a block that preforms reading of an input. CONSTITUTION:The acoustic signal supplied through an input terminal 2 divides the digital signals into a prescribed block length and writes them successively to a RAM7 with marks via a compressor 3, a sample and hold circuit 4, an A/D converter 5, a writing latch 6 and a marking circuit 10 and under the control of a write/read controller 8. A mark detecting circuit 21 detects a mark signal. Then two detection signals are produced between two mark signals (m), and the second detection signal is supplied to reading counters A14a and B14b synchronously with load signals j1 and j2. The address data given from latches C19 and D20 are sent to a RAM7 via a multiplexer 17, and the designated data is read out and delivered via D/A converters 24a and 24b, an integrator 25, an expander 26 and a filter 27.

Description

[Detailed Description of the Invention] [Industrial Field of Application] ” The present invention is a method of inputting an acoustic signal such as a musical tone signal and converting it into a PCM (
Performs processing such as encoding using pulse coding modulation),
The present invention relates to an audio signal time axis conversion device that performs encoded audio signal processing that changes the pitch of a musical tone or voice by compressing or expanding the time axis of the signal and outputting an audio signal.

[Prior art] As an audio device that processes musical tone signals and audio signals, an audio signal (original sound) is input, converted into a digital signal by processing such as PCM encoding, and this digital audio signal is divided into blocks and once When writing these signals to memory, compressing or expanding the time axis of each block, and reading them out, the associated blocks are repeatedly read and interlaced according to a predetermined procedure, so that the input acoustic signal is almost Development of an audio signal time axis conversion device using encoded audio signal processing that changes the pitch without changing the length of the sound in real time is underway.

However, in this type of time axis conversion device, it is necessary to perform processing such as repeated reading and skipping due to signal compression and expansion using a complex algorithm while checking the correlation of each signal block. It is impossible to process and output the time axis conversion process of such acoustic signals almost in real time while inputting the input signal, and the processing circuit becomes extremely complex. There was a problem.

On the other hand, if these algorithms are omitted and the device is simplified, the amount of information in the audio signal is significantly reduced, and there is a problem in that the sound quality, audibility, etc. of the decoded audio signal (playback sound) deteriorates.

[Objective of the Invention] The object of the present invention is to perform the process of changing the pitch without changing the length of the sound, that is, the time axis conversion process of compressing or expanding the acoustic signal, at a speed that is perceived as real time from an auditory perspective. An object of the present invention is to provide a time axis conversion device for an acoustic signal, which can obtain an acoustic signal with good clarity and hearing with a relatively simple circuit configuration.

[Configuration of the Invention] The configuration of the present invention made to achieve the above object is to input an analog audio signal and convert it into data using PCM.
- A PCM encoding means A for encoding a digital signal and a mark indicating a cut point on the digital signal corresponding to a predetermined same phase portion of the analog audio signal, thereby converting the digital signal into a predetermined code. encoded information writing means C that divides into block lengths and sequentially writes encoded information along a predetermined time axis into a readable/writable storage means B from a predetermined address; and encoded information stored in the storage means B. means for converting the time axis of the encoded information at a predetermined ratio and reading out the encoded signal from a predetermined address as an encoded signal for each block divided by marks attached to the encoded information; PCM decoding means E for decoding an encoded signal into an analog acoustic signal; - 6 - mark detection means that detects a mark attached to information and outputs an address setting signal based on the difference in mark detection interval during writing and reading; The latest address and the address immediately before it are temporarily stored among the addresses used when writing the encoded information attached to the storage means B, and the temporary address is stored in accordance with the address setting signal outputted by the mark detection means. The gist of the present invention is an acoustic signal time axis conversion device comprising: address setting means G for presetting one of the addresses stored in the block as the start address of a block to be read next; .

Embodiments of the present invention will be described below based on the drawings.

[Example] Figure 2 shows an analog audio signal such as a musical tone or voice input,
In addition to performing PCM encoding processing, the encoded signal is compressed without changing the length of the sound, that is, the playback speed, and time axis conversion with expansion is performed to subtly change the pitch of the reproduced sound of the decoded audio signal. C)-7- shows a block diagram of a time axis conversion device for an acoustic signal. Reference numeral 2 denotes an input filter that inputs and filters an analog audio signal such as a voice or a musical tone signal input from the input terminal 1, and sets a band by removing unnecessary frequency components and noise for audio signal processing. 3 is input filter 2
The compressor compresses the amplitude of the input signal sent from the decoding circuit, and compresses the signal amplitude for noise reduction operation.The expander of the decoding circuit, which will be described later, amplifies the signal. 4 is a sample/hold circuit that samples the analog acoustic signal sent from the compressor 3, and the instantaneous amplitude value of the continuous acoustic signal waveform is determined by the time interval of the sampling pulse sent from the write/sequence controller 8. is extracted as a sample value. A/5 quantizes the signal sampled by the sample/hold circuit 4 and converts it into binary encoded data.
It is a D converter. In this embodiment, the above filter 2
The A/D converter 5 constitutes PCM encoding means. 6 can read and write coded information (data) sent from the A/D converter 5 - 8 - Memory (RAM) 7 has a storage capacity equivalent to several blocks of acoustic signals. This is a write latch that latches to sequentially store data in a register, and the write/continuation controller 8
Temporarily stores data using a latch signal supplied from
When a write permission signal is sent to the RAM 7 from a multiplexer, which will be described later, encoded data is sent to the RAM 7 through the data bus, and the encoded data is sequentially written to designated addresses in the RAM 7.

9 is a cutting point of a block read from RAM 7 when writing encoded data to RAM 7, for example, when performing time axis conversion by compression/expansion of the signal on the least significant bit (LSB). This is a marking circuit that attaches a mark (for example, a code of logic "1") to designate the. The marking circuit 9 includes a zero-cross detection section that detects the analog acoustic signal as a zero-cross point during negative going when it is changed by the A/D converter 5, and outputs a marking command signal -9-. In response to this marking command signal, a mark (for example, a code of logic "1") indicating a block division point is added to, for example, the least significant bit (LSB) of the encoded data output from the A/D converter 5. A marking section is provided.

Reference numeral 10 denotes a timer circuit that masks the marking command signal output from the zero-cross detection section of the marking circuit 9 for a preset time and stops outputting the signal. A high-level masking signal is output to the zero-cross detection section for a predetermined masking time from the time of standing. The timer circuit 10 is provided with a second timer unit that operates when a silent input signal is input, and when the silent input signal continues, that is, for a long period of time when the marking at the cutting point specifying the block circulates through the memory. In order to eliminate cases where marking is not performed, if the marking command signal is not output from the zero-cross detection section of the marking circuit 9 even after the time set in the second timer section has elapsed, the marking circuit 9 is forcibly activated. It is configured to output a marking command signal to the marking section.

The above-mentioned write latch 6, a part of the write/read controller 8, the marking circuit 9, the timer circuit 10, etc. constitute encoded information writing means, and the digital signal converted by the A/D converter 5 is The above marks are applied to the data to divide it into predetermined block lengths, and the data is written to the storage means (in this case, the register of RAM 7) as encoded information along a predetermined time axis.In other words, the data input from terminal 1 The analog audio signal is sampled at a predetermined period, quantized, encoded, and stored in a register in the RAM 7 block by block.

Here, the length of the block read from the RAM 7 when performing time axis conversion is determined by the time interval of the mark indicating the cut point, that is, the scheduled time of the timer circuit 10, and the set time of this timer circuit is determined by the control The operation of the circuit 11 is controlled according to the degree of compression or expansion of the signal by time axis conversion, that is, the pitch ratio between the original sound and the -11- reproduced sound. In other words, if the length of the block during normal writing is constant, when time axis conversion is performed with the length of the reproduced sound constant, the block length of the read signal will change depending on the degree of compression or expansion of the signal. The number of cutting points changes greatly, but this control circuit 11 changes the length of the block at the time of writing so as to reduce the change in the number of cutting points in response to changes in pitch ratio. control. Therefore, the control circuit 11 detects the ratio between the period of the read clock signal i output from the variable clock signal generator 13 and the period of the write clock signal by multiplying the pitch ratio from the variable clock signal generator 13 by @10. , the ratio of this write/read cycle, that is,
When the pitch ratio between the original sound and the reproduced sound set by the pitch setting device 12, which is a pitch setting means, is large, that is, when the time axis is compressed, the timer circuit 10 is set according to the degree of compression (Tm in FIG. 4). On the other hand, if the set pitch ratio is small, the timer setting time T is increased accordingly.
It operates to shorten l11. This -12- control circuit 11 is actually a write/read controller 8.
It is constituted by one gate array together with a marking circuit 9, a timer circuit 10, etc.

The pitch setting device 12 is used to set the pitch ratio between the original sound and the reproduced sound in order to change the pitch of the reproduced sound to be higher or lower than the input sound, and its operation changes the reading speed of encoded data from the RAM 7. You can adjust the pitch to change the pitch without changing the length of the original sound. This pitch setter 12 is configured as a variable resistor provided in a variable clock signal generator 13 so as to change the period of successive clock signals 1 applied to read counters A14a and B14b.

15 is a clock signal generator that outputs a clock signal to the write/success controller 8 and the write counter 16;
A frequency-divided write clock signal for addressing the RAM 7 is sent to the write counter 16 . On the other hand, in the write/read controller 8, the clock signal generator 15
From the clock signal sent from the sample pulse signal a
) A/D conversion reference clock signal for A/D converter 5 -13- Switch signal C for writing No. 1, memory write enable signal d applied to RAM 7, memory read enable signal e1 read Latch signal '1+f2 and selection pulse signal 9 sent to multiplexer 17 for switching between write and read operations of RAM 7
are created respectively.

The timing of writing and reading encoded data into and from the RAM 7 is controlled so as to be performed continuously, for example, during one period of the write clock signal. ′
The write counter 16 is a ring counter that indicates a value corresponding to the address of the encoded data area in the RAM 7, receives a clock signal, counts, and sends the write address to the RAM 7 via the multiplexer 17. Therefore, when writing encoded data to the RAM 7, the encoded data is first temporarily stored in the write latch 6 by the write latch signal C sent from the write/read controller 8 to the write latch 6, and then transferred to the data bus. After being set, the write enable signal d to the RAM 7 is activated, and while the multiplexer 17 is switched to the write side, the write counter 16
The encoded data is sequentially written to the addresses specified by -14-.

Reference numeral 18 denotes a series controller that controls the latch C19 and the latch D20, and together with both the latches C19 and D20 constitutes an address setting means, which is equipped with a Noritsubu flop and gate of the type shown in FIG. The marking circuit 9 sends a marking signal 1yla.
is input, and the latchable signal 0゜q and strobe signals r and p synchronized with this marking signal Ma are latched C19.
is sent to the latch D20, and the latch C19 and the latch D20 are sent to the latch C19 and the latch D20 at the timing of the block division point indicated by the marking signal Ma.
temporarily stores the address information sent from the write counter 16 alternately.

21 is a mark detection circuit as mark detection means;
In addition to detecting the mark signal mf at the block division point attached to the encoded data that is sequentially written into the RAM 7, as shown in the timing chart of FIG. -15- detects a mark in encoded data and outputs a mark detection signal [)e, and when two mark detection signals []e are generated between two mark signals m, 2
A load signal n is generated in synchronization with the second mark detection signal @De. Then, this load signal n is divided into every other load signal @j1 and load signal j2, and the OR gate 21
1 to the two read counters via a and 21b, respectively.
4a and the read counter B 14 b, and the read counters A and B use the load signals @j + and j 2 to preset the address data at the beginning of reading by the latch C19 or the latch 020. The reason why such two readout counters A and B are used to read encoded data in two systems is to avoid skipping or repeated reading of encoded data at the signal block division point. This is to reduce noise caused by waveform shifts due to differences in signal pitch and amplitude when the envelope signals En A and En B, which are mutually inverted, are output from the envelope circuits 22 a and 22 b to the read latch A 23 a.

The encoded data from read latch B23b is -16 respectively.
- applied to the reference inputs of the two input D/A converters 24a and 24b, each block is not connected immediately, but gradually throttles its output once the previous data block has passed the cut point; , the new data block gradually increases its output from the cutting point, and the signals are connected at the block cutting point.

The above-mentioned 23a and 23b are read latches of two systems, respectively, and read latch signals f1 or f2 from the write/continuation controller 8 are sequentially inputted to the multiplexer 17 in synchronization with the read selection of the selection pulse signal 0. When switched to the read side, it latches the encoded data addressed by read counter A 14a or 814b and read from RAM 7 onto the data bus.

The above read counters A14a, B14b, multiplexer 17, read controller 18, latch 19.20
．． Mark detection circuit 21 and readout latches 23a, 23
b constitutes encoded signal reading means together with part -17- of the write/read controller 8.

24a and 24b are D/2 inputs the encoded signals latched by read latches A and B and converts them into analog signals.
The signals output from the D/A converters 24a and 24b are sent to an integrator 25 for integration, and then sent to an expander 26 to restore the signal amplitude compressed by the compressor 3 at input. and further output filter 2
7, and is configured so that an analog audio signal whose time axis has been converted and whose pitch has been changed can be obtained from an output terminal 28. The above D/A converters 24a and 24b.

The integrator 25, expander 26, and output filter 27 correspond to PCM decoding means.

Although not shown in the block diagram of Figure 2, it is not only possible to input the original sound such as a musical tone signal and simply change the pitch by time axis conversion processing and output it, but also to provide a mixer circuit on the output side to convert the original sound signal. By mixing and outputting a time-axis converted reproduced sound signal with a specific pitch ratio that forms a consonant interval with respect to the original sound, it is possible to create, for example, a 3rd -18= or 5th harmony from a single sound source. It is also possible to generate a consonant chord.

Also, by delaying the digital signal encoded and stored in the RAM 7 by a predetermined time and regenerating it, mixing it with the original sound signal and outputting it, it is possible to add an echo to the analog sound signal that is the original sound. It is also easy to apply.

Next, the operation of the time axis conversion device will be explained with reference to the waveform diagrams and timing charts of FIGS. 4 to 8. Here, FIG. 4 is a timing chart showing the marking operation of adding a mark to the encoded signal and setting the block length, and FIG. An explanatory diagram illustrating a graph illustrating the repeated readout process of some blocks of the encoded signal associated with this and a timing chart of each signal illustrating the operation, 6th
The figure shows the read control function as address setting means.
Figure 7 is a timing chart of each signal (Ma or latch C, D output) showing the operation of latches C19 and D20. FIG. 8 is an explanatory diagram showing a graph showing the skip processing of the block in the block and a timing chart of each signal (De to j2) showing its operation in correspondence, and FIG. 8 schematically shows the envelope of the input waveform of the integrator 25. This is the figure shown in . Each figure will be appropriately cited in the following description to further clarify the operation of the acoustic signal time axis converting device according to the embodiment of the present invention.

When using an audio signal time axis conversion device, first, the pitch setting device 12 sets the pitch ratio (tone interval ratio) between the input original sound and the output reproduced sound. For example, if the pitch ratio is set to 1:2, this means that the number of shots of the reproduced sound will be doubled compared to the original sound. For example, if the input musical sound signal is the sound of [C], the reproduction The sound is a "do" sound, which is an octave higher. By setting this pitch ratio, the period of the clock signal of the variable clock signal generator 13 is adjusted in inverse proportion to the pitch ratio based on the period of the fixed clock signal of the clock signal generator 15 sent to the writing side circuit. 20-, the reading speed increases in proportion to the pitch ratio with the signal writing surface as a reference.

When the pitch ratio is set and the device starts operating, the control circuit 11 outputs a fixed write clock signal output from the clock signal generator 15 and a read clock signal output from the variable clock signal generator 13. The period ratio of the clock signal @1 is detected by the pitch ratio signal 10, and based on the reciprocal of this period ratio, that is, the pitch ratio, if the pitch ratio is 1 or more, that is, when the signal is compressed, the timer circuit is activated according to the degree. The set time (Tn+) of the timer circuit 10 is lengthened, and conversely, when the signal is expanded when the pitch ratio is 1 or less, the set time (Tm) of the timer circuit 10 is shortened in accordance with the culm. By controlling the set time of this timer circuit 10,
Regardless of compression or decompression processing, the block length of the read signal is almost constant, and this may cause deterioration in sound quality due to an increase in block separation points during playback that occurs when compression processing is performed with a large pitch ratio, or when the pitch ratio is reduced. It is possible to eliminate delays in reproduced sound that occur during decompression processing.

= 21 = An acoustic signal such as a musical tone signal is input from an input terminal 1 , passes through an input filter 2 to remove frequency components and noise unnecessary for signal processing from the signal, and is sent to a compressor 3 . The compressor 3 compresses the amplitude of the acoustic signal for noise reduction, etc. The amplitude-compressed analog acoustic signal is sent to the PCM encoding processing circuit, and first,
The signal is input to the sample/hold circuit 4 and sampling is performed. Sampling is done by write/read controller 8
This is performed at the time interval of the sampling pulse signal a sent from the sampling pulse signal a, and each amplitude value is held as a sample value. The signal sampled by the sample-and-hold circuit 4 is then sent to the A/D converter 5, where it is encoded into binary numbers as quantized signal data. The encoded data of the acoustic signal converted into PCM code by the A/D converter 5 is then transferred to the write latch 6.
and is latched by a latch signal C supplied from the write/read controller 8. The encoded data latched by the write latch 6 is sequentially sent to the RAM 7, and is encoded in the RAM 7 while being addressed based on the address signal supplied from the write counter 16 through the marker 22-multiplexer 17. It is written in synchronization with the cycle of changes.

On the other hand, encoded data is transferred from the A/D converter 5 to the write latch 6.
When the encoded data is sent to and temporarily stored, a mark indicating the block division point of the signal is placed in the least significant bit of the encoded data at intervals based on the set time of the timer circuit controlled by the control circuit 11, and at intervals of the audio signal. It is given as follows at the zero cross position.

That is, as shown in FIG. 4, the acoustic signal S input from the input terminal 1 is converted into coded data by the A/D converter 5, but it is not binary coded data using complement representation. The most significant bit (MSB) represents the sign of the encoded data value. Therefore, when the most significant bit (MSB) of the encoded data changes from O to 1, the marking section of the marking ξ circuit generates a marking command signal U as a zero-crossing point of negative going.
−23 to the encoded data latched in write latch 6
- A mark indicating a block cutting point is attached to, for example, the least significant bit of the block, for example, as a logic "1" code.

Note that if the silent signal continues, the zero-crossing point of the acoustic signal cannot be detected and marking cannot be performed, but in such a case, the second timer section in the timer circuit 10 may After a set delay time from the falling edge of the signal V, the output signal is output to the zero-cross detection section, and a marking command signal is generated unconditionally, so that the mark indicating the block cutting point is placed in the encoded data in the same way as above. Granted to some. Of course, the set delay time of the second timer section is also controlled by the control circuit 1 in the same way as the mask time of the timer circuit 10.
1.

On the other hand, the encoded data stored in the RAM 7 is read out in real time according to a predetermined procedure while compressing or expanding the signal and at a reading speed based on the pitch ratio set by the pitch setting device 12 by the operation of the reading side circuit. The data is read out from the RAM 7 as follows.

-24- First, the case of increasing the pitch of reproduced sound by compressing the time axis and repeatedly reading out will be explained with reference to FIG. The graph in Figure 5 shows the change over time in the address of each counter for writing and reading, where the solid line Δ shows the change in address during writing, and the dashed-dotted line B shows the change in address during reading. , points a to f in the figure are marks of block division points during writing. In the mark detection circuit 21, a mark signal m indicating a mark attached to encoded data is inputted at the time of writing, and at the time of reading, the address of the read counters A14a and B14b is the address of the mark indicating this block division point (point a). A mark detection signal De is generated which becomes active when the mark detection signal De is reached. and,
The mark signal field at the time of writing and the mark detection signal [)e at the time of reading are compared, and two consecutive mark signals -
When two mark detection signals De are generated during this period, a load signal n is generated in the mark detection circuit 21 in synchronization with the second mark detection signal De. And load signal n
is divided into every other load signal J1 and load signal j2, which are sent to the two read counters A14a and B14b via the OR game 1-218.21b, respectively.
, B14b presets the address data latched by the latches C19 and D20, which is the start of the readout, by the load signals j1 and j2, and advances the count by the clock signal 1 according to the address. When the multiplexer 17 is switched to the read side by the selection pulse signal g sent from the write/read controller 8 to the multiplexer 17, the read enable signal e to the RAM 7 is activated, and the read enable signal e to the RAM 7 is activated. Encoded data is read out sequentially from the address.

In this way, when the slope of the dashed-dotted line B indicating the read speed is greater than the slope of the solid line A indicating the data write speed, that is, when compression of the time axis is performed, two marks are generated between successive mark signals l. When the detection signal De is generated, the previous block is repeatedly read out again to prevent the address of the read data from overtaking the address of the write data, and to achieve the minimum required value during time axis compression. By repeatedly reading out the limit blocks, the number of signal block connections is reduced and the audibility is improved.

The encoded data read from the RAM 7 and set up on the data bus is alternately latched by the read latch A23a and the read latch B23b by the read latch signals f, f2 output from the write/read controller 8. D/A converters 24a, 24-
sent to b.

In the D/A converters 24a and 24b, the differentially encoded signals are converted into analog signals, and each D/A converter is converted into an analog signal by the envelope signals EnA and EnB applied to the reference input.
The peaks of the waveforms of the analog signals at the beginning and end of the encoded data block output from the /A converters 24a and 24b have a slope of 9. 60-1 The amplitude is adjusted so that the amplitude changes from small to large at the beginning and from large to small at the end.Then, the two output signals are combined and sent to the integrator 25. is decoded into a complete analog signal by an expander 26, and then returned to the original signal amplitude by an expander 26, passed through an output filter 27, and sent to an output terminal 28.
An acoustic signal whose pitch has been raised by signal compression processing of time axis conversion is output from the signal.

On the other hand, when extending the time axis to lower the pitch of the reproduced sound (the pitch ratio is 1 or less), reading is performed by skipping blocks as shown in the graph of FIG. That is, the graph in FIG. 7 shows temporal changes in the addresses of each write and read counter, similar to FIG.
The solid line C shows the change in address during writing, and the dashed line shows the change in address during reading.In the figure, points a to f
is the mark of the block division point during writing. In the mark detection circuit 21, a mark signal m indicating a mark attached to encoded data is inputted at the time of writing, and at the time of reading, the address of the read counters A14a and B14b is the address (point) of the mark indicating this block division point. a to f)
28-- generates a mark detection signal [28-e] that becomes active. and,
This mark signal m during writing is compared with the mark detection signal during reading, and when two mark signals m are generated between two consecutive mark detection signals De, synchronization is made with the second mark detection signal @De. The load signal n is the mark detection signal 2.
1. Then, as in the case of time axis compression described above, every other load signal n is changed to load signal J+
, j2, each with two read counters A1
4a, B14b, and read counters A14a, B14b.
14b is this load signal j1. Latch C1 by Jz
9. Preset the read start address data sent from D20. Note that in the case of time axis expansion processing, the marking signal Ma input to the readout controller 18
is input to the 7 lip-flop without being inverted, and the latch enable signal 0. of FIG. q alternates at the rising edge of the marking signal Ma. Therefore, the address preset in the read counters A14a and B14b by the load signals j+ and J2 is not the address of the previous data, as in the case of compression processing, but the address of the latest block division point. Therefore, the ability to follow the original sound during reading is improved.

The preset read counters A14a and B14b advance the count from the address using the clock signal 1,
When the multiplexer is switched to the read side by the selection pulse signal 9 sent from the write/read controller 8 to the multiplexer 17, the read enable signal e to the RAM 7 is activated, and the read counters 14a, 14
Encoded data is read from the address specified by b. In this way, when the time difference between read processing and write processing becomes large, the time axis is extended without changing the length of the sound by skipping one block and reading the next block. , processing to lower the pitch is performed. Then, similarly to the compression process described above, the read encoded data is alternately latched for each series of blocks by the read latches A23a and B23b, decoded and synthesized by the decoding circuit, and output as an analog audio signal. -30- This produces a lower pitched playback sound.

Furthermore, as mentioned above, the envelope of the signal sent to the integrator 25 during decoding can be schematically expressed as D/
The A converter 24a outputs a signal as shown in (I), and similarly, the D/A converter 24b outputs a signal as shown in (I), for example.
A signal as shown in II) is output, and the integrated integrator 25
The input signal has a shape represented by (I[I).

In this embodiment configured as described above, the mark indicating the cutting point attached to the encoded signal is detected, and when the time axis is expanded (lower the pitch), the encoded information is When two or more marks for writing are detected between two consecutive marks detected during reading, the latest stored address is set as the start address of the next read so as to skip the previous block. If you want to compress the time axis (increase the pitch), set f in advance to compress the time axis (increase the pitch). When detected, the previous block is read out again, and the address immediately before the latest stored address is set in advance as the next read address. Therefore, according to this embodiment, when compressing or expanding the time axis of an audio signal, the latest encoded information written in the RAM can be decoded while performing repeated reading or skipping processing associated with this. Since it is possible to perform time axis conversion processing in real time, it is possible to convert the pitch of musical tones and voices in real time, and to obtain output signals with good clarity and audibility with a relatively simple circuit configuration. It can be widely used to generate consonance with the original sound, or to generate special sounds.

Furthermore, since the acoustic signal is encoded by PCM, the acoustic signal level at the block joint during repeated reading of blocks during decoding or reading skipping is almost zero, so other encoding methods, such as Compared to encoding methods such as DPCM and 6M that take the difference between acoustic signals, the seam is located at the peak value of the acoustic signal.
It is possible to perform time axis transformation of an acoustic signal with a low distortion rate over a wider frequency band. For example, each encoding means is a PC.
In acoustic signal time axis converters having the same configuration except for whether M or DPCM is adopted, the frequency band is 4d in the DPCM method.
Even if B down is allowed, it is only 40H2~8Kt-1z, but in PCM system, even 3dB down is 20H2~8Kt-1z.
It covers the band from H2 to 8.5KH2. Also, the total harmonic distortion rate was 1.7% in the DPCM method, but was less than 0.5% in the PCM method.

This is because in the DPCM method, although the peak value of the acoustic signal is not necessarily the same, the rate of change of the acoustic signal is zero and the signals can be connected most smoothly. This is thought to be because the signals are connected at irregular peak points, and the difference between them causes signal distortion, which limits the frequency band.

This problem was solved by adopting the PCM method.

Also, the PCM method was compared with the 6M and DPCM methods.
In the case of 3-, since no difference is taken, the sharp attack of the acoustic signal can be reproduced more faithfully, and there is also the advantage that there is less delay in the sound perceptually.

Furthermore, since two A/D converters are used in this embodiment, the envelope of the signal sent to the integrator 25 during decoding is determined by the D/A conversion, as schematically shown in FIG. The D/A converter 24a outputs a signal such as (I>), and the D/A converter 24b outputs a signal (II), for example.
A signal as shown by is outputted, and the input signal of the integrated integrator 25 has a shape shown by (III). Therefore, the seams between blocks during decoding are eliminated so that they are not noticeable to the listener.

Note that in this embodiment, the write/continuous output controller 8.
Marking circuit 9. Although the timer circuit 10 and the control circuit 11 are constructed by a single gate array together with other peripheral gates and the like in order to increase the control speed, they can also easily be constructed by a microcomputer that performs processing at a sufficiently high speed.

-34- Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments in any way, and it goes without saying that it can be implemented in various forms without departing from the gist of the present invention. be.

[Effects of the Invention] As described in detail above, the audio signal time axis conversion device of the present invention encodes an analog audio signal using PCM, divides it into blocks, writes the encoded information into a storage means, and stores it in a predetermined manner. Read the encoded signal from the storage means according to the procedure P
In an audio signal time axis conversion device configured to perform CM decoding and output an audio signal whose pitch has been changed, when writing and reading encoded information to and from the storage means, the encoded information is f mark detection means for detecting the attached marks and outputting an address setting signal based on the difference in mark detection intervals during writing and reading; -35- of the addresses when writing to the storage means, the latest address and the address immediately before it are temporarily stored, and the temporary storage is performed according to the address setting signal outputted by the mark detection means. The present invention is characterized by comprising: address setting means for presetting any one of the addresses as the start address of a block to be read next.

Therefore, when compressing or expanding the time axis of an audio signal, it is possible to decode the latest encoded information written in the storage means while performing repeated readout or skipping processing, almost in real time. Since time axis conversion processing can be performed, the pitch of musical tones and voices can be converted in real time, and an excellent effect can be achieved in that an output signal with good clarity and audibility can be obtained with a relatively simple circuit configuration. In addition, PCM
Since the acoustic signal is encoded and decoded using the method, the attack can be faithfully reproduced, and it is also possible to perform time conversion of the acoustic signal with a low distortion rate over a wide frequency band.

[Brief explanation of the drawing]

-36- Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is a block diagram of an acoustic signal time axis conversion device as an embodiment, Fig. 3 is a circuit diagram of the readout controller 18, Fig. 4 5 is a timing chart showing the marking operation of adding a mark to the encoded signal and setting the block length, and Figure 5 shows the processing when compressing the audio signal and the accompanying encoding as an example of time axis conversion of the audio signal. FIG. 6 is an explanatory diagram showing a graph showing the process of repetitive reading of a part of a block of signals and a timing chart of each signal showing its operation in correspondence. FIG. The signal timing chart, Figure 7, corresponds to a graph showing the process of expanding the audio signal and the accompanying process of skipping some blocks of the encoded signal, and a timing chart of each signal showing the operation. FIG. 8 is a diagram schematically showing the envelope of the input waveform of the integrator 25. 4...Sample/hold four paths -37- 5...A/D converter 6...Write latch 8...RAM 9...Marking circuit 10...Timer circuit 11...Control circuit 12...Pitch setting device 16...Writing counters 14a, 14b...Reading counters 24a, 24b ・D/A converter agent Patent attorney Tsutomu Sadatsu and 1 other person -38- Figure 3 18 Figure 4 Timer rotation S operation force Vl ml Fig. 5 Fig. 6 7 items n a b c d Fig. 7

Claims (1)

[Claims] 1. PCM encoding means for inputting an analog audio signal and encoding it into a digital signal using PCM; encoded information writing means that divides the digital signal into predetermined block lengths by marking the blocks, and writes the encoded information sequentially from a predetermined address into a read/write storage means as encoded information along a predetermined time axis; , a code that converts the time axis of the encoded information stored in the storage means at a predetermined ratio and reads out the encoded information from a predetermined address as an encoded signal for each block divided by marks attached to the encoded information; In the audio signal time axis converting device, the audio signal time axis converting device is provided with a PCM II encoding means for decoding the read coded signal into an analog audio signal -1-, mark detection means for detecting a mark attached to the encoded information when writing and reading the encoded information and outputting an address setting signal based on a difference in mark detection interval during writing and reading; An address that temporarily stores the latest address and the address immediately before it among the addresses used when the encoded information writing means writes the encoded information marked with a mark into the storage means, and outputs the mark detection means. an address setting means for presetting any one of the temporarily stored addresses as the start address of the next block to be read in accordance with a setting signal; Axis conversion device. 2. The mark detection means detects two consecutive marks when reading encoded information from the storage means, while detecting two marks when writing encoded information to the storage means -2- At this time, an address setting signal for continuous skipping is output as an address setting signal, and while two consecutive marks are detected when writing encoded information to the storage means, the encoded information is read from the storage means. When two marks are detected, the address setting signal is configured to output an address setting signal for repeated repeating, and when the address setting means inputs the address setting signal for repeating repeating, the address setting signal is temporarily stored. On the other hand, when the repeat address setting signal is inputted, the address immediately before the temporarily stored latest address is set in advance as the start address of each block to be read next. An apparatus for converting an acoustic signal between II and axial axis according to claim 1, which is configured as follows.