JPH04306018A - Counter circuit - Google Patents

Abstract

PURPOSE:To count clocks at a high speed after a data is inputted. CONSTITUTION:A shift register SR is in feedback connection and a data at an 8-th shift register 3H is given to a 5-bit counter 4 as a count object. A data to the shift register SR is shifted by each clock 1 and 3-bit outputs 8A, 8B, 8C of an encoder 20 are changed in response to the clock 1. The data to the shift register SR is shifted and circulated and every time the data is given to the 8-th shift register 3H, the 5-bit counter 4 is incremented and counts 8D, 8F, 8G, 8H in 5 bits of the 5-bit counter 4 are changed in response to the data of the shift register 3H. Then an 8-bit count data is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit that counts clocks at high speed when a predetermined signal is input.

0002

2. Description of the Related Art Data processing in digital circuits is performed by digital operations or logical operations by logic circuits. Such data processing is performed by logical operations such as AND, OR, and NOT, in which "high" and "low" voltages in the digital circuit correspond to binary values of "1" and "0". Some counter circuits used in such digital circuits start a counting operation when data is input, and count the clock after the data is input. FIG. 3 shows this type of conventional counter circuit, which is constructed using an 8-bit counter 18. 8 bit counter 18
are a data input terminal LD to which data 2 is input, a clock input terminal CLK to which clock 1 is input, and data output terminals Q1, Q2, Q3, Q4, Q5, Q6, Q7.
, a carry output terminal Q8, and an initial value input terminal LV. and data output terminals Q1, Q2, Q3, Q
8-bit count data 8 from 4, Q5, Q6, Q7
A, 8B, 8C, 8D, 8E, 8F, 8G, and 8H are output, and a carry signal 8I is output from the carry output terminal Q8.

FIG. 4 is a block diagram showing the internal configuration of the counter circuit shown in FIG. 3. The counter circuit consists of 8 1
Bit counter 19A, 19B, 19C, 19D, 19
It consists of E, 19F, 19G, and 19H. Each of the 1-bit counters 19A, 19B...19H includes a clock input terminal CLK, a data input terminal LD, an initial value input terminal LV, and a carry output terminal C. Further, each of the 1-bit counters 19A, 19B . . . 19H is provided with a data output terminal Q0, Q1 . Clock 1 is input to the clock input terminal CLK of the first stage 1-bit counter 19A, and the carry signal from the carry output terminal C is input to the clock input terminal CLK of the second stage 1-bit counter 19B. The carry signal of the carry output terminal C of the second stage 1-bit counter 19B is the carry signal of the third stage 1-bit counter 1.
The carry signal from the carry output terminal C is input to the clock input terminal CLK of the fourth stage 1-bit counter 19D. The carry signal of the carry output terminal C of the 1-bit counter 19D in the 4th stage is transmitted to the 1-bit counter 19D in the 5th stage.
The carry signal from the carry output terminal C is input to the clock input terminal CLK of the sixth stage 1-bit counter 19F. The carry signal of the carry output terminal C of the 6th stage 1-bit counter 19F is the carry signal of the 7th stage 1-bit counter 19G.
The carry signal from the carry output terminal C is input to the clock input terminal CLK of the eighth stage 1-bit counter 19H. A carry signal BI is output from the carry output terminal of the 8th stage 1-bit counter 19H. 1-bit counter 19A, 19B...19H each data input terminal L
Data 2 is commonly input to D, and a ground potential is commonly applied to each initial value input terminal LV. In addition, count data 8A, 8B is output from each data output terminal Q0, Q1...Q7 of 1-bit counter 19A, 19B...19H.
...8H is output.

Next, the operation of this counter circuit will be explained. Now, after initializing the output data 8A, 8B...8H of the 1-bit counters 19A, 19B...19H, the clock input terminal CLK of the first stage 1-bit counter 19A is
When clock 1 is input to , its carry output terminal C becomes "0" at the first clock, and "0" at the second clock.
1”. And the first stage 1-bit counter 19A
When a carry signal is input to the clock input terminal CLK of the second-stage 1-bit counter 19B, the first carry signal causes the carry output terminal C of the 1-bit counter 19B to become "0", and the next carry signal causes it to become "0". 1”. In other words, the carry terminal C of the first-stage 1-bit counter 19A becomes "1" every two clocks input thereto, and the second-stage 1-bit counter 19B
is its carry terminal C every 4 clocks of clock 1.
becomes "1". In this way, the carry signal of the second-stage 1-bit counter 19B is input to the third-stage 1-bit counter 19C, and the carry signal is input to the fourth-stage 1-bit counter 19D.
Input to 9E, 19F, 19G, 19H.

As a result, the third stage 1-bit counter 19
The carry output terminal C of C is output every 8 clocks of clock 1, the carry output terminal C of the 4th stage 1-bit counter 19D is output every 16 clocks of clock 1, and the carry output terminal C of the 5th stage 1-bit counter 19E is output every 16 clocks of clock 1. The carry output terminal C of the 1-bit counter 19F in the 6th stage is carried out in units of 64 clocks of clock 1, and the carry output terminal C of the 1-bit counter 19G in the 7th stage is carried out in units of 128 clocks of clock 1. In clock units, the carry output terminal C of the 8th stage 1-bit counter 19H becomes "1" in units of 256 clocks of clock 1. In this way, each of the 1-bit counters 19A, 19B...19H performs a counting operation in response to clock 1, and the respective count data 8A, 8B are output from the data output terminals Q0, Q1...Q7 of the 1-bit counters 19A, 19B...19H. ...Outputs 8H. Further, when data 2 is input to the data input terminal LD, the count data of each of the 1-bit counters 19A, 19B, . . . , 19H becomes the initial value. As a result, count data 8A, 8B, . . . 8H of clock 1 from the time when data 2 was input is output.

[0006]

By the way, a conventional counter circuit is constructed by connecting in series one-bit counters of the same number as the number of bits of count data. Therefore,
When constructing a counter circuit with a large number of bits of count data, the number of 1-bit counters connected in series will inevitably increase. However, since carry signals propagate between serially connected 1-bit counters, and a predetermined propagation time is required, the higher the number of serially connected 1-bit counters, the faster the counting operation becomes. There is a problem with being blocked. In view of this problem, it is an object of the present invention to provide a counter circuit that can perform counting operations at high speed even when obtaining count data with a large number of bits.

[0007]

[Means for Solving the Problems] A counter circuit according to the present invention uses a predetermined signal as shift data and a counting clock as a shift clock, and includes a plurality of stages of shift registers connected in feedback, and a reset signal as the predetermined signal. It is configured to include a counter that counts data in a predetermined stage of a shift register, and an encoder that encodes data in each stage of the shift register except for a specific stage.

[0008]

[Operation] When a predetermined signal is input, the shift register and the counter are reset, data is obtained only in the shift register of a specific stage, and the shift register becomes an initial state. Data is shifted in accordance with the clock, and data in the shift registers of each stage except for a specific stage is input to the encoder, which outputs clock count data. When the data is shifted to a shift register at a predetermined stage, the counter is incremented, and the counter outputs clock count data. The output value of the encoder becomes the lower bits of the clock count value, and the count value of the counter becomes the upper bits of the clock count value. Therefore, when shifting the data of the shift register, the propagation time of the carry signal is not required, so if the count data is obtained by the shift register and the encoder, the time for the counting operation is shortened.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a counter circuit according to the present invention. The counter circuit is a 5-bit counter 4
, an eight-stage shift register SR, and an encoder 20. Clock input terminal C of 5-bit counter 4
Clock 1 is input to LK, and its reset terminal R
Data 2 is input to ST. Data output terminal Q0
, Q1, Q2, Q3, and Q4 output 5-bit count data 8D, 8E, 8F, 8G, and 8H, and a carry signal 8I is output from the carry output terminal Q5. Each shift register 3A, 3B, 3C, 3D, 3E, 3F, 3G from the 1st stage to the 8th stage of the shift register 10,
Clock 1 and data 2 are input to 3H. 8
The data in the shift register 3H at the first stage is input to the shift register 3A at the first stage, and also to the data input terminal LD of the 5-bit counter 4. In this way, the shift register SR is connected in a feedback manner so that the data of the eighth stage shift register 8H is inputted to the first stage shift register 3A.

Each encoder 20 has a 4-input OR circuit 5.
, 6, and 7, and the 4-input OR circuit 5 includes shift registers 3E, 3F, 3G, and 3H from the fifth stage to the eighth stage.
Each data is input. The 4-input OR circuit 6 includes shift registers 3C, 3 in the 3rd, 4th, 7th, and 8th stages.
D, 3G, and 3H data are input. 4 input OR
The circuit 7 receives data from the second, fourth, sixth, and eighth shift registers 3B, 3D, 3F, and 3H. Three-bit count data 8A, 8B, and 8C are output from four-input OR circuits 7, 6, and 5.

FIG. 2 is a block diagram showing the configuration of the shift register SR. FIG. 2(a) shows the first stage shift register 3A, and FIG. 2(b) shows the respective stages from the second to the eighth stage. Shift register 3B, 3C, 3D, 3E, 3F, 3G
, 3H is a block diagram. 1st stage shift register 3
A consists of a 1-bit shift register 11 and an OR circuit 10, and a clock input terminal CLK of the shift register 11
Clock 1 is input to , and latch data 12 is output from output terminal Q. Data 2 and latch data 9 of the shift register 3H are input to the OR circuit 10, and the
The output of the R circuit 10 is input to the input terminal D of the shift register 11. This shift register 3A is configured to set the value of the shift register 11 to "1" when data 2 is input thereto.

The shift registers 3B, 3C, . . . , 3H other than the first stage shift register 3A consist of a 1-bit shift register 16, an inverter 14, and an AND circuit 15, and the clock input terminal C of the 1-bit shift register 16
Clock 1 is input to LK, and latch data 17 is output from output terminal Q. Data 2 is input to the inverter 14, and its output is A
It is input to one input terminal of the ND circuit 15. The latch data 13 of the previous stage shift register is input to the other input terminal of the AND circuit 15, and the output of the AND circuit 15 is 1.
It is input to the input terminal D of the bit shift register 16. This shift register 16 is configured to set the value of the shift register 16 to "0" when data 2 is input thereto.

Next, the operation of the counter circuit configured as described above will be explained. Now, data 2 is in shift register SR
When the signal is input to the 5-bit counter 4, the shift register SR and the 5-bit counter 4 are reset and start counting. At this time, the first stage shift register 3
The value of A is set to "1" by data 2, and the values of the other shift registers 3B, 3C, . . . , 3H remain reset to "0". And shift register 3A,
3B...The shift register data is "1" among 3H
There is only one shift register SR, and the shift register SR is initialized. Each time a clock is input after initialization, the data "1" in the shift register 3A is sequentially shifted to the second, third,...eighth shift registers 3B, 3C, . . . , 3H. The data in shift register 3B is “1”
”, the count data 8A which is the output of the OR circuit 7
becomes “1” and the data of shift register 3C becomes “1”
Then, the count data 8B, which is the output of the OR circuit 6, becomes "1".

Furthermore, the data in the shift register 3D is "1"
Then, the count data 8 which is the output of the OR circuits 7 and 6
Both A and 8B become "1". According to the number of clocks input in this way, count data 8A, 8B,
8C changes, and count data of the input clock is obtained by shift register SR and encoder 20. And the 8th clock is shift register S
When input to R and the 5-bit counter 4, the data in the shift register 3G is shifted to the shift register 3H, and the data becomes "1", which is input to the data input terminal LD of the 5-bit counter 4. The 5-bit counter 4 increments, and the count data 8D output from the data output terminal Q0 becomes "1".

Furthermore, at the 9th clock, the data in the 8th stage shift register 3H is shifted to the 1st stage shift register 3A, and the data in the shift register 3A becomes "1" again. After that, the data is shifted in the same manner as described above. “1” of register 3A
" data is sequentially shifted to the 3H side in accordance with the clock. In this way, the data in the shift register SR goes around once every 8 clocks, and every 8th clock, the 5-bit counter 4
is incremented, and the count data 8D, 8E, 8F, 8G, and 8H of the 5-bit counter 4 change. The output value of the encoder 20 becomes the lower bits of the clock count value, and the count value of the 5-bit counter 4 becomes the upper bits of the clock count value.

In this way, the shift register SR and the encoder 20 obtain the count data of the lower bits consisting of 3 bits of the clock count value, and the 5-bit counter 4 obtains the count data of the upper bits consisting of 5 bits of the clock count value. Count data is obtained, and from them 8
A counter circuit that can obtain bit count data can be realized. If the clock count data is obtained by the counter in this way, and the clock count data is also obtained by the shift register and encoder, the shift register does not have the propagation of a carry signal like a counter, so it can be used as a shift register. The clock can be counted at high speed using an encoder. Furthermore, if the number of bits of the count data to be output is the same, a counter with a smaller number of bits by the number of bits of the count data output from the encoder can be used, so that the counter can also count the clock at high speed. This makes it possible to speed up the clock counting operation after data input. Furthermore, the greater the number of bits of count data to be output, the more remarkable the effect of speeding up the counting operation.

In this embodiment, 3-bit count data is obtained from the encoder, but this is just an example, and a counter that outputs an appropriate number of bits and a shift register with an appropriate number of stages can be used. Of course, the present invention is not limited to this embodiment.

[0018]

As described in detail above, the counter circuit of the present invention uses a predetermined signal as shift data and a clock as a shift clock, and uses a plurality of feedback-connected shift registers to shift the predetermined signal as a reset signal. Since it is equipped with a counter that counts data in a predetermined stage of the register and an encoder that encodes the data of the shift register in each stage except for a specific stage, when performing a counting operation using the shift register and encoder, it is possible to use The time required for the propagation of the carry signal is not required, and the time for the counting operation is shortened. Further, since a counter having a smaller number of bits than the number of bits of the clock count value can be used as the counter, the time required for the counting operation by the counter is shortened. Therefore, even when obtaining count data with a large number of bits, there is an excellent effect of providing a counter circuit that can count clocks at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a counter circuit according to the present invention.

FIG. 2 is a block diagram showing the internal configuration of a shift register.

FIG. 3 is a block diagram showing the configuration of a conventional counter circuit.

FIG. 4 is a block diagram showing the internal configuration of the counter circuit in FIG. 3;

[Explanation of symbols]

4 5-bit counter 5, 6, 7
4-input OR circuit SR shift register 11, 16
1 bit shift register 20
encoder

Claims (1)

[Claims] 1. A counter circuit that counts clocks when a predetermined signal is input, the predetermined signal being shift data and the clock being a shift clock, comprising a plurality of feedback-connected shift registers; A counter uses a predetermined signal as a reset signal, and includes a counter that counts data in a predetermined stage of a shift register, and an encoder that encodes data in each stage of the shift register except for a specific stage. A counter circuit characterized in that the counter circuit is configured as a bit, and the data of the counter is used as the upper bits of the counted value.