JPH04307687A - Memory storage circuit - Google Patents

Abstract

PURPOSE:To miniaturize the scale of the circuit and to shorten the reproducing time from the memory by storing two kinds of the data, sampling data and random data, in a memory. CONSTITUTION:When the sampling is normally performed, a data writing circuit and a counter circuit 5 are started by a sampling timing signal 103 outputted from a timer circuit 3c and writing data 109 composed of sampling data 1 and the sampling time data 101 are stored in the writing address within a memory 12a outputted from the counter circuit 5 in accordance with a pulse signal 104 from the data writing circuit 4. When random data 2 is generated, the data is temporarily stored in a register circuit 11, and a timer circuit 3c outputs the passing time data 107 to the register circuit 11 and makes the circuits 4, 5 start. The circuits 4, 5 write writing data 109 composed of random data 2 and the passing time data 107 within the pertinent block of the memory 12a.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage circuit for storing periodically sampled data and irregularly generated random data.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing the configuration of a conventional memory storage circuit. FIG. Figure (b) shows a circuit portion that stores random data that occurs irregularly and the time of its occurrence as a set.

In FIG. 6(a), reference numeral 1 indicates sampling data that is sampled periodically, 3a indicates a sampling timing and a timer circuit that generates the sampling time, and 4 transfers the sampling data 1 and its time data 101 to a memory 6. 5 is a counter circuit that generates a write address 105 to the memory 6; and 6 is a memory that stores the sampling data 1 and its time data 101.

In the figure, 101 is the timer circuit 3a.
102 is the write data stored in the memory 6, 103 is a sampling timing signal for the timer circuit 3a to activate the data write circuit 4 and the counter circuit 5, 104 is the data A data write pulse signal outputted from the write circuit 4 to the memory 6; 105 is the counter circuit 5;
This is the write address signal generated by the memory 6, and as shown in FIG. 7(a), the configuration of the memory 6 is as shown in FIG. , tc, and td and are stored in association with each other.

On the other hand, in FIG. 6(b), 2 is random data that occurs irregularly, and 3b is the random data 2.
a timer circuit 7 that generates the generation time of the random data 2; a data write circuit 7 that is activated by the generation of the random data 2 and outputs a data write pulse signal 104 to the memory 8;
8 is the random data 2 and its occurrence time data 10
The counter circuit 5 is activated by a data write pulse signal output from the data write circuit 7.

First, the configuration of the memory 8 is as shown in FIG. 7(b), in which random data A is stored in each block 10.
, B, and C are stored in correspondence with their occurrence time data tA, tB, and tC.

Next, the operation will be explained. First, when storing sampling data 1 (FIG. 6(a)), when the timer circuit 3a outputs the sampling timing signal 103 to the data write circuit 4 and the counter circuit 5 to activate them, the data write circuit 4 A data write pulse signal 104 is outputted so that write data 102 consisting of sampling data 1 and time data 101 generated by the timer circuit 3a is stored at an address generated by the counter circuit 5 (given to the memory 6 by a signal 105); The counter circuit 5 increments an internal counter. Thereafter, the above-described operation is repeated at regular sampling timing.

On the other hand, when storing random data 2 (
6(b)), when random data 2 is generated, the data write circuit 7 is activated and outputs the data write pulse signal 104 to the memory 8. The generation of this data write pulse 104 causes the counter circuit 5 to By outputting the address signal 105 to the memory 8 (after the output, the internal counter is incremented), the write data consisting of the random data 2 and the generation time data 101 generated by the timer circuit 3b is written to the memory 8.
It will be stored in . Thereafter, the above-described operation is repeated every time random data 2 is generated.

[0009]

[Problem to be Solved by the Invention] Since the conventional memory storage circuit is configured as described above, hardware such as dedicated memory is required for two types of data: sampling data and random data. However, as the circuit scale becomes larger, data reproduction from the memory must be performed for each memory storing each data, which causes problems such as time consuming.

[0010] This invention was made to solve the above-mentioned problems, and by storing two types of data, sampling data and random data, in one memory, it is possible to reduce the size of the circuit and also to It is an object of the present invention to obtain a memory storage circuit that makes it possible to shorten the time for reproducing data from a memory.

[0011]

[Means for Solving the Problem] The memory storage circuit according to the invention of claim (1) divides the inside of the memory for data storage into blocks, and divides the sampling data and the sampling data into blocks for each block. While storing the time in association with each other, random data that occurs irregularly between the current sampling and the next sampling within the same block is also stored.
The elapsed time from the current sampling time is stored in association with the current sampling time.

Further, the memory storage circuit according to the invention of claim (2) is the memory storage circuit according to the invention of claim (1), in which a plurality of sampling data acquisition lines are provided and random data is temporarily stored. A plurality of register circuits are provided, and a plurality of sampling data and a plurality of sampling data are stored in each memory block.

[0013] Furthermore, the memory storage circuit according to the invention of claim (3) uses a FIFO memory or a shift register as the memory in the memory storage circuit according to the invention of claims (1) and (2). This configuration eliminates the need for a counter circuit that generates .

[0014]

[Operation] In the invention of claims (1) to (3), the memory is equally divided into blocks, and one memory is divided into blocks in the same block.
Or, since it is configured to store two types of data, two or more sampling data and one or more random data, in association with the time, each data can be managed and identified by block or time, and only one memory is required. This can be achieved with

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a memory storage circuit according to an embodiment of the invention of claim (1), and the same or equivalent parts as in the conventional memory storage circuit (FIG. 6) are given the same reference numerals and explained. omitted.

In the figure, 3c is a timer circuit that generates the sampling timing signal 103 and the sampling time data 101, as well as elapsed time data 107 until the generation of the random data 2, and 11 is the timer circuit that generates the random data 2 and the immediately preceding sampling. The register circuit 12a temporarily stores the elapsed time data 107 from the time to the generation of the random data 2, and the register circuit 12a stores the write data 109 consisting of the sampling data 1 and its time data 101, or the random data 2 and its elapsed time data 107. This is memory stored in equally divided blocks 13a.

In the figure, 107 is the timer circuit 3c.
108 is data consisting of the random data 2 and its elapsed time data outputted from the register circuit 11; 109 is data generated from the memory 12;
As shown in FIG. 2, this memory 12a associates sampling data a, b, c, d and sampling time data ta, tb, tc, td with equally divided blocks 13a. At the same time, the random data B and D generated from the current sampling to the next sampling are stored as elapsed time data αB, α from the previous sampling time (the time when the current sampling was performed).
D and stored in the block 13a corresponding to each sampling data 1.

Next, the operation of the invention according to claim (1) will be explained. Normally, when sampling is performed, the sampling timing signal 1 output from the timer circuit 3a
03, the data write circuit 4 and the counter circuit 5 are started, and the write data 109 consisting of the sampling data 1 and its sampling time data 101 is sent to the write address in the memory 12a (as a signal 105 to the memory 12a), which is output from the counter circuit 5. (given) according to the data write pulse signal 104 output from the data write circuit 4. After outputting the address signal 105, the counter circuit 5 increments the internal counter to indicate the write address of the random data 2 that will be generated until the next sampling. However, if the random data 2 is not generated, , the value of the internal counter is incremented at the next sampling time to make it the address where sampling data 1 is stored.

On the other hand, when random data 2 is generated before the next sampling, it is temporarily stored in the register circuit 11, and the timer circuit 3c outputs the elapsed time data 107 from the previous sampling time to the register circuit 11, and the data write is completed. The circuit 4 and the counter circuit 5 are activated, and the random data 2 and its elapsed time data 1 are similarly generated.
The write data 109 consisting of 07 is written into the corresponding block 13a of the memory 12a. At this time, the register circuit 11 that outputs the data 108 for writing erases its memory contents, increments the internal counter of the counter circuit 5, and sets it as the write address of the sampling data 1 obtained by the next sampling, and thereafter operates as described above. Repeat for each block.

Next, an embodiment of the invention of claim (2) will be described. FIG. 3 is a block diagram showing the configuration of a memory storage circuit according to an embodiment of the invention according to claim (2). The invention of claim (2) provides that the memory storage circuit (FIG. 1) according to an embodiment of the invention of claim (1) has a
2a, one sampling data 1 and one random data 2 are stored in the same block 13a, but the configuration is such that a plurality of each data can be stored.

[0021] Therefore, a plurality of sampling data 1a~
In order to input 1 m, m (≧2) input lines are provided, and n (≧2) register circuits 11a to 11n are provided to input a plurality of random data 1a to 1n. As shown in FIG. 4, each equally divided block 13b contains a plurality of sampling data a1, a2, ..., an and its sampling time data ta, and a plurality of random data A1, A2, ..., A.
m and the respective elapsed time data αA1, αA2, ...
, αAm.

Next, an embodiment of the invention of claim (3) will be described. FIG. 5 is a block diagram showing the configuration of a memory storage circuit according to an embodiment of the invention according to claim (3). The invention of claim (3) is based on the invention of claim (1) and (2).
) memory storage circuit according to an embodiment of the invention (FIGS. 1 and 3)
FIFO memories or shift registers are used as the memories 12a and 12b in ), and thus the configuration does not require a counter circuit 4 for instructing a write address in advance.

[0023]

As described above, according to the invention as claimed in claim (1), the memory for data storage is equally divided so that each block can store two types of data, sampling data and random data. According to the invention of claim (2), by providing a plurality of acquisition lines for inputting sampling data and a plurality of register circuits for temporarily storing random data, a plurality of sampling data and a plurality of sampling data can be stored in each block in the memory. Since the memory is configured to store random data, and according to the invention of claim (3), a FIFO memory or a shift register is used as the memory so that a counter circuit for generating a write address is not required. Two types of data, sampling data and random data, can be stored in one memory, the scale of the memory storage circuit can be reduced, and each data can be easily managed and identified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory storage circuit according to an embodiment of the invention as claimed in claim (1).

FIG. 2 is a diagram showing the configuration of a memory in a memory storage circuit according to an embodiment of the invention of claim (1).

FIG. 3 is a block diagram showing the configuration of a memory storage circuit according to an embodiment of the invention as claimed in claim (2).

FIG. 4 is a diagram showing the configuration of a memory in a memory storage circuit according to an embodiment of the invention as claimed in claim (2).

FIG. 5 is a block diagram showing the configuration of a memory storage circuit according to an embodiment of the invention as claimed in claim (3).

FIG. 6 is a block diagram showing the configuration of a conventional memory storage circuit.

FIG. 7 is a diagram showing the configuration of each memory in a conventional memory storage circuit.

[Explanation of symbols]

1 Sampling data 2 Random data 3c Timer circuit 4 Data write circuit 5 Counter circuit 11 Register circuit 12a, 12b Memory

Claims (3)

[Claims] [Claim 1] Two types of data are divided into blocks by dividing them into equal parts in advance, and two types of data are collected: sampling data that is regularly sampled for each block, and random data that occurs irregularly between the current sampling and the next sampling. a timer circuit that generates a sampling time and an elapsed time from the sampling time to a random occurrence as a time to be stored in the memory; and a timer circuit that stores the randomly generated random data as a set. , a register circuit that temporarily stores the elapsed time generated by the timer circuit; a counter circuit that generates a write address to the memory in accordance with an activation instruction of the timer circuit; A memory storage circuit comprising: a data write circuit that writes the sampling data and random data to a generated address on the memory. [Claim 2] There are two types of sampling data: a plurality of sampling data that are divided into blocks in advance and sampled regularly for each block, and a plurality of random data that are irregularly generated from the current sampling to the next sampling. a timer circuit that generates a sampling time and an elapsed time from the sampling time to the random occurrence as the time to be stored in the memory; a plurality of register circuits, each of which temporarily stores a plurality of random data along with an elapsed time generated by the timer circuit; a counter circuit that generates a write address to the memory in accordance with an activation instruction of the timer circuit; A memory storage circuit comprising: a data write circuit that writes each of the plurality of sampling data and the plurality of random data to an address on the memory generated by the counter circuit according to an activation instruction of a timer circuit. [Claim 3] Two types of data are divided into blocks by dividing them into equal parts in advance, and the sampling data sampled regularly for each block and the random data that occurs irregularly between the current sampling and the next sampling are combined. A FIFO memory or a shift register is used as a memory for storing time in association with each other as a set, and a sampling time and an elapsed time from the sampling time to a random occurrence are generated as the time to be stored in the FIFO memory or shift register. a timer circuit, and the irregularly generated random data, together with the elapsed time generated by the timer circuit,
A memory storage circuit comprising: a register circuit for temporarily storing data; and a data write circuit for sequentially writing the sampling data and random data into the FIFO memory or shift register according to an activation instruction from the timer circuit.