JPS6148221A - Delay data generator - Google Patents

Abstract

PURPOSE:To obtain a delay data generator with less memory capacity by providing the 1st memory storing data by a data number, the 2nd memory storing the data number and the 3rd memory storing data outputted after a prescribed time. CONSTITUTION:The data number from a control circuit 1 is given to the 1st memory 2 storing data and 2nd memory 3 storing the data number. The memory 2 used the number as an address to read the data and outputs it from a terminal 10. The memory 3 receives the data number as write data and stores it in a write address increased by 1 at each clock period T. A data delay time nT is stored in a register 6 for the (n), a subtractor 7 subtracts the value of the register 6 from the value of the counter 5 and the value is given as the read address of the memory 3. The memory 3 gives the data number given from the circuit 1 to the 3rd memory 4 after the time nT and the similar data as that in the memory 2 is outputted from a terminal 11 of the memory 4 after the time nT. Thus, the memory capacity required for the delay is less.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a nine-delay data generation device using a memory.

(Conventional technology) Conventionally, in this type of delayed data generation device.

If data is output sequentially and the data is needed again after a certain period of time, use the memo +7 for data delay.
A method is used in which the data is provided inside the device, and the data is sequentially stored in the memory at the same time as the data is output, and the data is read out and output after a certain period of time has elapsed.

Here, the clock cycle of the device is tT, and the data cycle is tT.

Assuming that the number B and the required delay time are 1nxT, the capacity required for the data delay memory is expressed as Bxn.

Therefore, there is a drawback that as the number of data bits or delay time increases, the memory capacity increases significantly.

(Objective of the Invention) The object of the present invention is to store data in a first memory, read and output the data using a given data number as an address, and store the data number in a second memory depending on luck. After a certain period of time has elapsed, it is taken out again and given as an address to the third memory.

The purpose of the third memory is to provide a delayed data generating device with a small memory capacity that reads and outputs data according to a given data number.

(Structure of the Invention) The device of the present invention includes a first memory that outputs pre-stored data based on a given data number, and a second memory that sequentially stores the data number and outputs it after a certain period of time has elapsed. 2
and a third memory that outputs data stored in advance according to the data number output from the second memory.゛(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The delayed data generator shown in FIG. 1 includes a control circuit 1 that provides a data number, a first memory 2 and a third memory 4 that output data according to the given data number, and is used for the purpose of delaying all data numbers. and a second memory 3 that can be read and written at the same time.

A counter 5 that provides a write address to the second memory 3
, a register 6 that indicates a delay time, and a subtracter 7 that obtains a read address from the values of the counter 5 and the register 6 and supplies it to the second memory 3. It is assumed that this delayed data generator operates in synchronization with a clock having a period T.

A data number for outputting required data is given by the control circuit 1 to the first memory 2 and the second memory 3. The first memory 2 performs a read operation using this data number as an address, and outputs the read data to the terminal 10. On the other hand, the second memory 3 receives this data number as all write data, and stores it in a write address that is incremented by 1 every cycle T by the counter 5. Here, if the time required for data delay is nXT, register 6
Let n=i be held in advance. The subtracter 7 subtracts the value of the register 6 from the value of the counter 5 and provides the value to the memory 3 as a read address.

Therefore, the memory 3 has the same address 'I!' as the write address given by the counter 5! It will be given as a read address after ``nxT'' time.

As a result, control circuit 1] given data number 1! −
It will be given to the third memo S4 after nx'r time. The third memory 4, like the first memory 2, exposes all data using the data number as an address.

Output from terminal 11.

With the above operation, this delayed data generator has terminal 1
The same data as that outputted from terminal 11 is outputted from terminal 11 after a predetermined delay time has elapsed.

Here, in this embodiment, the memory capacity required for data delay is the number of data pits B, the total delay time nxT, the number of data N, and the smallest integer that is greater than or equal to (#ogN+log2). Letting b be the bit width of the second memory 3, it is expressed as (BxN+nxb). In the conventional case, it is expressed as BXn as described above, so the larger B and n become.

Alternatively, the effectiveness of the present invention becomes more significant as the number N of data decreases.

As an example, the number of data bits is 144 bits.

Considering that the delay time is 64T or less and the required number of data is 16 words, in the conventional case, 144x64 due to data delay.
= 9216 bits of memory is required; in this example, b is 4, so 144x16+4x64=2
560 bits of memory is sufficient.

Note that in this embodiment, the first memory 2 and the third memory 4
It is not necessary that the data stored in the third memory 4 be the same as that of the first memory 2, and data that is different from the first memory 2 is stored in the third memory 4, and certain data is output from the terminal 10, and after a certain period of time, the corresponding data is stored in the third memory 4. Other data can also be output from the terminal 11.

The second memory 3 of this embodiment is a FIFO buffer with a delay time of T;
If you use F, the counter 5. It is clear that register 6 and subtractor 7 are no longer needed.

(Effects of the Invention) The present invention has the following advantages. Second. The provision of the third memory has the effect that the memory capacity can be significantly reduced compared to the first system by storing data numbers in a delayed manner.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Control circuit, 2... First memory, 3
...Second memory, 4...Third memory,
5...Counter, 6...Register, 7.
...Subtractor, 10.11...Output terminal.

Claims (1)

[Scope of Claims] A first memory that outputs pre-stored data according to a given data number; a second memory that sequentially stores the data number and outputs it after a certain period of time has elapsed; and the second memory. and a third memory for outputting pre-stored data according to the data number output from the delay data generator.