JPH0431212B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal reproducing device for reproducing digital signals.

Conventional configurations and their problems In recent years, development of digital audio equipment that applies digital technology to the consumer field, mainly in the audio industry, has become active. FIG. 1 shows the format of a digital signal recorded on a record carrier such as a disk or tape in such a digital audio device. The data 2 to be finally reproduced as an audio signal is divided into blocks for each unit time together with an error correction code for correcting data errors caused by scratches on the record carrier, etc., and synchronization is established with the beginning of each block. Synchronization signal 1 for
is recorded with the addition of This one block will be called one frame. To read such digital signals, it is known that
Bit synchronization is achieved using a PLL circuit, etc., and this
It uses the bit clock that is the output from the PLL circuit. This makes it possible to determine whether the logical value is "1" or "0". Next, synchronization signal 1 is detected and sent to the synchronization circuit together with the bit clock for frame synchronization. FIG. 2 shows a configuration diagram of a conventional digital signal reproducing device. In FIG. 2, first, the digital signal 3 read from the record carrier is transmitted to the PLL circuit 4.
The signal is then input to a synchronization pattern detection circuit 5 that detects a synchronization pattern of a predetermined synchronization signal.
The PLL circuit 4 outputs the bit clock 4a. The output 5a of the synchronization pattern detection circuit 5 is AND
The signal passes through the gate 6 and is input to the synchronization detection and determination circuit 7. A synchronization detection determination circuit 7 outputs a synchronization detection signal 7a when a synchronization signal is detected, and outputs a synchronization non-detection signal 7b when a synchronization signal is not detected to a counter 8.
Or output to counter 9. When the counters 8 and 9 count up to their respective predetermined values, they output a carry signal 8a or 9a, and a reset flip-flop (hereinafter referred to as
(referred to as SR-FF) 10. Output 10a of SR-FF10 is R gate 11
is input to. On the other hand, the timing of the gate signal generation circuit 12 is adjusted by the synchronization detection signal 7a,
A gate signal 12a is outputted through the R gate 11 to N the AND gate 6 for a certain period of time before and after the time when the synchronization signal of the next frame is to be detected. The timing generation circuit 13 also performs timing alignment using the synchronization detection signal 7a, and outputs an internal synchronization signal 13a necessary for synchronization detection determination to the synchronization detection determination circuit 7.

The operation of the synchronous circuit configured as above is explained in the third section.
This will be explained using the timing charts shown in FIGS. First, in FIG. 3, the synchronization signal 1 of the digital signal 3 input to the synchronization pattern detection circuit 5 is
Therefore, the output 5a is generated in timing with the end of the synchronization signal 1. On the other hand, the gate signal 11a puts the AND gate 6 in the N state for a certain period of time before and after the output 5a. The purpose of this is to prevent a digital signal with the exact same pattern as sync signal 1 from occurring where sync signal 1 should not exist due to a dropout (hereinafter referred to as dropout) of digital signal 3 caused by scratches on the record carrier, etc. This is to prevent erroneously detecting this as a correct synchronizing signal, thereby disturbing the operation of the synchronizing circuit and causing data errors. Next, the output 7a of the synchronization determination circuit 7 is output 5.
Occurs at the same timing as a. When the synchronizing signal is lost and not detected due to dropout D or the like as in the third frame, an output 7b is generated. The timing of the internal synchronization signal 13a is adjusted by the synchronization detection signal 7a output one frame before, and is generated at the timing when the bit clock 4a is counted by a number corresponding to one frame. Further, the gate signal 11a is the SR-
If the output 10a of FF10 is the logical value "0",
It is clear that this signal is the same as the output 12a of the gate signal generation circuit 12, and the timing of this output 12a is also adjusted by the synchronization detection signal 7a output one frame before, like the internal synchronization signal 13a, and the bit clock The output 5a of the synchronization pattern detection circuit 5 is generated only for a short period before and after the output 5a of the synchronization pattern detection circuit 5 should be generated at a timing corresponding to the period in which 4a is counted by a number corresponding to one frame. If the synchronization signal is not detected due to dropout D or the like, timing is adjusted using the internal synchronization signal 13a. Next, the operations of the counters 8 and 9 will be explained using FIG. 4.
Each counter is used to determine whether synchronization has been established or synchronization has been lost. That is, the counter 8 now has a count value of "2" and the carry signal 8a is
On the other hand, if the counter 9 is set to output the carry signal 9a with a count value of "3" and there is a dropout _D1 over three frames in the digital signal 3, then the above SR-FF1
The output 10a of 0 outputs a logical value of "1" when the carry signal 9a is output. When the output 10a has a logic value of "0", it indicates that synchronization has been established, and when the output 10a has a logic value of "1", it indicates that synchronization has been lost. Generally, in the digital signal reproducing apparatus as described above, if a synchronization signal is not detected a predetermined number of times in a row, it is determined that synchronization has been lost. This is not only due to the presence of a dropout in the digital signal 3 and the inability to detect the synchronization signal, but also due to the above-mentioned
Due to a phenomenon called cycle slip occurring in the PLL circuit 4, a dropout occurs in a part of the digital signal 3, disrupting bit synchronization, and even though the synchronization signal itself is not erroneous, the gate signal generation circuit 12 and timing generation circuit 1
3 is disturbed by excessive or insufficient generation of the bit clock 4a, and as a result, the gate signal 12a is generated at the wrong timing when the output 5a of the synchronization pattern detection circuit 5 cannot be gated, resulting in a state in which the synchronization signal cannot be continuously detected. This is because things happen. The timing disturbance caused by this cycle slip is usually about ±1 to 3 bit clocks, so taking this into account, the width of the gate signal 12a is set to ±1 to ±3 bit clocks with respect to the output 5a of the synchronization pattern detection circuit 5.
It is set to about 5 bit clocks. On the other hand, the set values of counter 8 and counter 9 are set in consideration of the correction ability of the error correction code, and counter 8 is set to "1" or "2", and counter 9 is set to a value that can be sufficiently covered by the correction ability, for example, for 8 consecutive frames. A value of "6" or "7" if error correction is possible, and a value exceeding "8" if the final reproduced audio signal does not become audibly unpleasant due to interpolation etc. even if the error correction capability is exceeded. It may also be set to . however,
If interpolation is performed continuously, the sense of distortion may increase to some extent.

As mentioned above, in the conventional configuration, if the cycle slip of the PLL circuit 4 exceeds ±5 bit clocks even once due to dropout, etc., the synchronization will go out of synchronization even if there is no error in the digital signal. There is a problem in that data errors occur consecutively for the number of frames set for out-of-synchronization determination, and in some cases, audibly unpleasant sound is reproduced.

Purpose of the invention The present invention solves the above-mentioned conventional problems.
It is an object of the present invention to provide a digital signal reproducing device that can reduce continuous data errors due to out of synchronization caused by cycle slips in a PLL circuit.

Structure of the Invention The present invention includes a synchronization pattern detection circuit that detects a synchronization signal from a digital signal to which the synchronization signal is added, a loss detection circuit that detects a loss of the digital signal, and an output from the synchronization pattern detection circuit. A gate signal generation circuit generates a gate signal that gates the output of the synchronization pattern detection circuit for a certain period of time before and after the synchronization signal is detected after timing is adjusted, and when the synchronization pattern detection circuit does not detect the synchronization signal. The out-of-synchronization judgment circuit counts the generated out-of-synchronization detection signals and generates a signal indicating out-of-synchronization when a predetermined set value is reached, and the out-of-synchronization judgment circuit generates a signal indicating out of synchronization based on the output of the digital signal loss detection circuit. By controlling the set value of , continuous data errors due to loss of synchronization can be reduced.

DESCRIPTION OF THE EMBODIMENTS FIG. 5 is a block diagram of a digital signal reproducing apparatus according to an embodiment of the present invention. In Figure 5,
PLL circuit 4, synchronization pattern detection circuit 5, AND gate 6, synchronization detection judgment circuit 7, counter 8, SR
-FF 10, R gate 11, gate signal generation circuit 12, and timing generation circuit 13 have the same configuration as the conventional example. The counter 14 counts the synchronization non-detection signal 7b and outputs the output 6a of the AND gate 6.
It is cleared with . The decoder 15 decodes two types of values for the output 14a of the counter 14 and inputs the outputs 15a and 15b to the selector 16. This selector 16 is controlled by an output 17a of a digital signal loss detection circuit 17. The counter 14, decoder 15, and selector 16 constitute an out-of-synchronization determination circuit.

The operation of the digital signal reproducing apparatus of this embodiment configured as described above will be explained. First, it is configured by inputting the digital signal 3 of the omission detection circuit 17 and detecting a portion in a state that does not match the modulation method (for example, 3PM, etc.), or by digitizing it immediately after it is obtained from the record carrier as is known. It consists of performing envelope detection on the signal that is not detected, and detecting the missing part based on the amplitude change.

This will be explained below using the timing chart shown in FIG. The set value at which the carry signal 8a of the counter 8 is output is "2", and the decoder 15 outputs the carry signal 8a of the counter 14.
Decodes the output 14a of ``2'' and outputs 15a.
, outputs output 15b at "6", and selector 16
The output 17a of the missing detection circuit 17 is the logical value "φ"
It is assumed that the decoder output 15b is selected when the logic value is "1", and the decoder output 15a is selected when the logic value is "1". Digital signal 3 causes a data error over 3 frames due to dropout D ₂ , and PLL
If the circuit 4 causes a cycle slip around time t= _tA and the amount exceeds -5 bit clocks, the output 11a of the R gate 11 after that occurs at a timing that is relatively delayed from the timing at which the correct synchronization signal is detected. Occurs in In the conventional case, no correct synchronization signal would be detected, resulting in out-of-synchronization, and all six frames of data set for out-of-synchronization determination would be erroneous. However, in this embodiment, when the counter 14 counts the synchronization non-detection signal 7b twice, the output 17a of the digital signal loss detection circuit 17 has a logical value of "1", so the selector output 16a indicates that the synchronization is out of synchronization. A signal with a logical value of "1" is output. This output 1
SR-FF10 is set by 6a, and as a result, the output 11a of the OR gate 11 becomes a logical value "1", and the AND gate 6 continues to be N. Therefore, a correct synchronizing signal can be detected again at time t=t _B immediately after the dropout ends. As described above, according to the present invention, by controlling the selector 16 using the output of the digital signal loss detection circuit 17 and changing the conditions for determining out-of-synchronization, data errors of 6 frames due to cycle slips would normally occur. The number of data errors can be reduced to three frames.

Effects of the Invention The present invention prevents extremely long consecutive data errors due to loss of synchronization caused by cycle slips in the PLL circuit by controlling the set value of the out-of-sync determination circuit using the output of the digital signal loss detection circuit. An advantage of being able to suppress data errors to a relatively short length, preventing the occurrence of data errors that exceed the correction ability of the error correction code and moving to interpolation, and preventing the reproduction of aurally unpleasant sounds. This makes it possible to realize a digital signal reproducing device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the format of a digital signal, FIG. 2 is a configuration diagram of a conventional digital signal reproducing device, and FIGS. 3 and 4 are timing charts for explaining the operation of a conventional digital signal reproducing device.
FIG. 5 is a block diagram of a digital signal reproducing apparatus according to an embodiment of the present invention, and FIG. 6 is a timing chart for explaining the operation of the digital signal reproducing apparatus. 5... Synchronization pattern detection circuit, 12... Gate signal generation circuit, 14... Counter, 15... Decoder, 16... Selector, 17... Missing detection circuit.

Claims (1)

[Claims] 1. A device that reproduces a digital signal in which a synchronization signal of a certain bit pattern is added to block data every unit time,
A loss detection circuit detects the loss of this digital signal, a synchronization pattern detection circuit detects the synchronization signal from the digital signal, and the output from this synchronization pattern detection circuit performs timing alignment, and the synchronization signal is detected. a gate signal generation circuit that generates a gate signal that gates the output of the synchronization pattern detection circuit for a certain period of time before and after the synchronization pattern detection circuit;
comprising an out-of-synchronization determination circuit that counts a synchronization non-detection signal generated when a synchronization signal is not detected by the synchronization pattern detection circuit, and generates a signal indicating out of synchronization when a predetermined set value is reached;
A digital signal reproducing device characterized in that a setting value of the out-of-synchronization determination circuit is controlled by an output of the digital signal loss detection circuit.