JPH04313255A - Formation of interconnection - Google Patents

Abstract

PURPOSE:To increase the stability of the process in which a W (tungsten) plug is formed on an Al lower-layer interconnection and to increase the adhesion of the W plug. CONSTITUTION:The surface part of the base, an Al-1% Si layer, is etched isotropically through a connection hole 13 which is made in a layer-to-layer insulated film 12 to form an undercut-shaped recessed part 13a. That time, readhering matters 14, 15 of the Al-1% Si layer 11 are also removed. Nextly, the H2 reduction selective CVD is conducted to fill the reessed part 13a with a first selective W layer 16 and then the SiH4 reduction selective CVD is conducted to fill the connection hole 13 with a second selective W layer 17. The first and second selective W layers 16 and 17 are united into one body to form a plug part 18. The plug part 18 has an excellent adhesion with the interlayer insulated film 12 due to its form effect. By removing the readhering matters 14, 15 beforehand, W is allowede to grow uniformly by a selective CVD.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a wiring forming method applied in the field of manufacturing semiconductor devices, etc., and in particular to a stable method for selectively growing a conductive material layer that will become a plug portion on a lower wiring layer through a connection hole. The present invention relates to a method that makes it possible to improve conductivity, improve adhesion of conductive material layers, reduce contact resistance, etc.

0002

2. Description of the Related Art As semiconductor devices become more highly integrated and performant, as seen in VLSI, ULSI, etc. in recent years, the proportion of wiring on device chips tends to increase. In order to prevent a significant increase in chip area due to this, multilayer wiring has now become an essential technology. As a method for forming wiring, it has conventionally been widely used to form an aluminum (Al)-based metal material layer by sputtering. However, as mentioned above, as wiring becomes more multilayered and as a result, the surface steps of the substrate and the aspect ratio of connection holes increase, the lack of step coverage in the sputtering method Poor connections between upper layer interconnects and semiconductor substrates and between interconnects have already become serious problems.

Therefore, in recent years, a so-called plug forming technique has been proposed in which a high melting point metal such as tungsten (W) or its silicide is buried in the connection hole by CVD. In particular, among the above-mentioned CVD methods, there is a method in which a high melting point metal layer or its silicide layer is selectively grown only inside the connection hole by utilizing the underlying layer exposed at the bottom of the connection hole and the reducing property of the additive gas. The CVD method is a technology that is highly expected to be put into practical use. Tungsten (W) has been well studied as the above-mentioned high melting point metal, and can be used on the surface of silicon substrates or Al-based material layers, or on H2 or silane (
W is reduced by reducing WF6 with an additive gas such as SiH4).
A typical example is the process of depositing

0004

[Problem to be solved by the invention] However, the selective CVD
The mechanism of this method has not yet been fully elucidated, and deposition conditions, the film quality and surface condition of the interlayer insulating film, reaction by-products, etc. are complexly influenced, and the process tends to cause deterioration of uniformity and failure of selectivity. . For example, the base A sputtered inside the connection hole
If the l-based material layer is redeposited, uniform growth will be inhibited. This phenomenon will be explained with reference to FIGS. 8(a) and 8(b). FIG. 8(a) shows an Al plate with steps.
An interlayer insulating film 22 made of silicon oxide (SiO2) is formed substantially flat on the lower-layer wiring 21, and a first contact hole 23 and a second contact hole 24 having mutually different depths are opened in the interlayer insulating film 22. It shows the state that has been applied. These connection holes 23 and 24 are formed by performing RIE (reactive ion etching) on the interlayer insulating film 22.
Such anisotropic etching of SiO2 proceeds by a strongly ionic mechanism. Therefore, when the etching of the interlayer insulating film 21 is almost completed, the exposed Al-based lower wiring 2
High-energy ions are incident on the contact hole 1, and the sputtered Al-based material adheres to the side walls of the connection holes 23 and 24 to form a film-like redeposit 25 and a particulate redeposit 26. In particular, since the Al-based lower layer wiring 21 is exposed earlier in the shallow second connection hole 24 than in the deep first connection hole 23, the amount of re-deposition increases, resulting in the so-called aluminum crown ( This causes the formation of aluminum crowns.

[0005] While such redeposited substances 25 and 26 are present, W is deposited into the connecting holes 23 and 24 by selective CVD.
When attempting to grow the W layer 27, the re-deposited substances 25 and 26 serve as growth nuclei, causing the W layer 27 to grow non-uniformly as shown in FIG. cause trouble. Another problem is that the adhesion of the W layer 27 to the interlayer insulating film 22 decreases. Moreover, even if the above-mentioned re-deposition materials 25 and 26 are not formed, it is almost impossible to fill the connection holes 23 and 24 having different depths flatly by the selective CVD method. For example, as shown in FIG. 9, under the condition that the deep first connection hole 23 is buried almost flat, the shallow second connection hole 2
4, excessive growth part 27a commonly called nail head
will occur.

[0006] In addition, the influence of by-products in the CVD reaction system also poses a problem. For example, in the above example, the connection hole 23,
Since WF6 is reduced by the surface of the Al-based lower layer wiring 21 exposed at the bottom of the aluminum fluoride (AlF)
3) is a by-product. However, as is clear from the fact that even the melting point of this AlF3 is as high as 1291°C, CVD
It is difficult to volatilize and remove because the vapor pressure in the reaction system is extremely low, and it is an insulating material. Therefore, AlF3
If it remains at the interface between the Al-based lower layer wiring 21 and the W layer 27, it will cause an increase in contact resistance. Therefore, the present invention provides a wiring formation method that enables improved stability when selectively growing a conductive material layer on a lower wiring material layer through connection holes, improved adhesion of the conductive material layer, and reduced contact resistance. The purpose is to provide a method.

[0007]

[Means for Solving the Problems] The wiring forming method of the present invention is proposed in order to achieve the above-mentioned object, and includes filling connection holes opened in an insulating film on a lower wiring layer with a conductive material layer. The method comprises: isotropically etching a portion of the lower wiring layer in the layer thickness direction through the connection hole to form a recess whose opening end is larger than the periphery of the connection hole. a step of selectively growing a first conductive material layer in at least the recess; and a step of selectively growing a first conductive material layer in at least the recess;
The method is characterized in that it has a step of filling with a layer of conductive material.

[0008]

[Operation] The main point of the present invention is to isotropically etch a portion of the lower wiring layer in the layer thickness direction prior to forming the conductor material layer. This isotropic etching is performed for the purpose of cleaning the inside of the connection hole and improving adhesion due to the shape effect. That is,
Under conditions for isotropically etching the lower wiring layer, re-deposit material made of the same material is also removed at the same time, so that non-uniform nucleation can be avoided when at least the first conductive material layer is selectively grown in the subsequent process. There is no risk of this happening. Further, in the present invention, the recess formed by isotropic etching has a so-called undercut shape directly under the insulating film. When this recess is filled by selective growth of a first layer of conductive material and the connection hole above it is filled with a second layer of conductive material, both layers form a structurally integrated plug section. do. In other words, the plug portion appears to be wedged into the lower wiring layer through the connection hole.

[0009] Here, it is assumed that the first conductive material layer is evenly embedded in the recesses having an undercut shape. Academic Conference of Japan Society for Applied Physics (1990)
Autumn) Lecture Proceedings Volume 2 668 pages, Presentation Number 2
Published on 8a-SZD-15. This study showed that even when a SiN overhang is formed above the contact hole in the selective CVD method, the contact hole is filled flatly by the W layer at almost the same deposition rate as when there is no overhang. It is something. The above eaves are WF6 in the selective CVD method.
It was intentionally formed to suppress the diffusion of WF6, focusing on the fact that the rate-determining process is the period from when WF6 reaches the substrate surface to when the reduction reaction occurs. In this invention,
The lower end of the insulating film plays the same role as the eaves described above, and the recesses are quickly and uniformly filled.

On the other hand, the second conductive material layer may be formed on the entire surface of the substrate by a blanket CVD method, a sputtering method, etc., or it may be selectively formed only inside the connection hole by a selective CVD method, etc. . In any case, since redeposited matter inside the connection hole is removed by the above-described isotropic etching, uniform film formation can be performed.

[0011] Particularly when applying the blanket CVD method, it has traditionally been a problem that the W layer formed by this method has poor adhesion with the insulating film. It has been considered essential to prevent peeling by interposing an adhesion layer consisting of. However, in this case, if over-etching is performed in the etch-back process, the adhesive layer inside the connection hole is etched intensively due to the loading effect, which deteriorates the filling characteristics of the connection hole. According to the present invention, since the conductor material layer is fixed to the lower wiring layer due to the above-mentioned shape effect, an adhesive layer is formed between the insulating film and the conductor material layer (especially the second conductor material layer). Peeling of the conductor material layer can be prevented even without intervening. Therefore, the embedding characteristics are not deteriorated in the etch-back process. Also,
When blanket CVD is applied, even if contact holes with different depths exist, they can be flattened by etchback, so there is no need to worry about nail heads remaining like when selective CVD is applied. .

Of course, the second conductive material layer can be formed by selective CVD.
It may be formed by law. In this case, if the type of wiring material is the same, the step of forming the first conductive material layer can be performed as a continuous step. The selective CVD method is
Conventionally, it has been pointed out that as the film formation time increases, the factors that destabilize the process increase, but according to the present invention, one of the factors, re-deposition inside the connection hole, is removed in advance. , it is possible to form a film with far better controllability than in the past.

[0013]

[Examples] Specific examples of the present invention will be described below. Example 1 In this example, the lower wiring layer is an Al-1%Si layer, the first conductive material layer and the second conductive material layer constituting the plug part are both made of W, and the first conductive material is This is an example in which the layer is formed by a selective CVD method using SiH4 reduction, and the second conductor material layer is formed by a blanket CVD method. This process will be explained with reference to FIGS. 1-5.

FIG. 1 shows an Al-1%Si layer 1 having steps.
There is an interlayer insulating film 2 made of silicon oxide (SiO2) on top.
The figure shows a state of a wafer in which a first contact hole 3 and a second contact hole 4 having mutually different depths are opened in the interlayer insulating film 2, and the interlayer insulating film 2 is formed substantially flat. The Al-1% Si layer l sputtered by incident ions during patterning of the interlayer insulating film 2 is reattached to the side wall of the second contact hole 4, which is relatively shallow among these contact holes 3 and 4, and the film Redeposited matter 5 in the shape of a shape and redeposited matter 6 in the form of particles are formed.

The above wafer is set in a parallel plate type plasma etching apparatus, and as an example, a Cl2 flow rate of 30S is set.
The surface layer portion of the Al-1% Si layer 1 was isotropically etched under the conditions of CCM, gas pressure of 80 Pa (0.6 Torr), and RF power density of 0.2 W/cm 2 (13.56 MHz). As a result, as shown in FIG. 2, recesses 3a and 4a were formed at the bottoms of the first connection hole 3 and the second connection hole 4, respectively, with opening ends larger than the periphery thereof. At the same time, redeposited substances 5 and 6 were removed from the side wall of the second connection hole 4.

Next, the above wafer is transferred to a CVD apparatus, and as an example, WF6 flow rate is 10SCCM, SiH4 flow rate is 7SCCM, H2 flow rate is 1000SCCM, and gas pressure is 27.
Selective CVD was performed under conditions of Pa (0.2 Torr) and substrate temperature of 260°C. In this process, the diffusion of WF6 to the outside is suppressed to some extent at the lower end of the interlayer insulating film 2, so that WF6 is transferred to Al-1 in the recesses 3a and 4a.
% was reduced while uniformly contacting the surface of the Si layer 1. As a result, the recesses 3a and 4a were filled with the selective W layer 7, as shown in FIG. At this time, since the redeposited matter 5 and 6 had been removed from the side wall of the second connection hole 2 in advance, no abnormal nuclear growth occurred.

Next, as an example, WF6 flow rate 60SCC
M, H2 flow rate 360SCCM, gas pressure 10640Pa
Blanket CVD was performed under conditions of (80 Torr) and a substrate temperature of 475°C. As a result, as shown in FIG. 4, the entire surface of the wafer is covered with the blanket W.
Layer 8 was formed. At this time, the blanket W layer 8 is grown on the already formed selective W layer 7 and is structurally integrated therewith, so that the adhesion to the interlayer insulating film 2 is good even without providing a particular adhesion layer. Met.

Next, the above wafer is transferred to a parallel plate type plasma etching apparatus, and as an example, the SF6 flow rate is 3.
0SCCM, Cl2 flow rate 10SCCM, gas pressure 2Pa
(15mTorr), RF power density 0.25W/cm
2 (13.56MHz) with the above blanket W
Layer 8 was etched back. As a result, as shown in FIG. 5, the insides of the first connection hole 3 and the second connection hole 4 were filled substantially flat with the buried W layer 8a, and the plug portion 9 was completed.

Example 2 In this example, the first conductive material layer and the second conductive material layer constituting the plug portion are both made of W, and the first conductive material layer is selected to utilize H2 reduction. This is an example in which the second conductive material layer is formed by a selective CVD method using SiH4 reduction. This process will be explained with reference to FIGS. 6(a) to 6(d).

FIG. 6(a) shows Al-1% lower layer wiring.
A connection hole 13 is opened in the interlayer insulating film 12 on the Si layer 11, and a film-like re-deposition 14 and a particulate re-deposition 15 originating from the Al-1%Si layer 11 are formed on the side wall of the connection hole 13. The state of the wafer is shown in which a wafer is formed.

The above wafer is set in a magnetic field microwave plasma etching apparatus, and as an example, a Cl2 flow rate of 30 SCCM, a gas pressure of 2.1 Pa (16 mTorr),
Microwave power 800W, RF bias power 20
The surface layer portion of the Al-1% Si layer 11 was isotropically etched under the condition of W (2 MHz). As a result, Figure 6(b)
As shown in FIG. 1 , a recess 13 a was formed at the bottom of the connection hole 13 in the form of an undercut below the interlayer insulating film 12 . At the same time, the redeposited substances 14 and 15 were removed from the side wall of the connection hole 13.

Next, the above wafer is transferred to a CVD apparatus, and as an example, WF6 flow rate is 5SCCM, H2 flow rate is 500
Selective CVD was performed under the conditions of SCCM, gas pressure of 20 Pa (0.15 Torr), and substrate temperature of 410°C. Here H2
The reason for performing the reduction is to suppress the generation of AlF3 due to the reaction between WF6 and the Al-1%Si layer 11, and to prevent an increase in contact resistance and non-uniform growth of W. As a result, as shown in FIG. 6(c), the recess 1
3a is uniformly filled with the first selected W layer 16.

Next, as an example, WF6 flow rate 10SCC
M, SiH4 flow rate 7SCCM, H2 flow rate 1000S
Selective CVD was performed under the conditions of CCM, gas pressure of 27 Pa (200 mTorr), and substrate temperature of 260°C. S like this
The reason why iH4 reduction is performed is that the reduction reaction of WF6 by SiH4 is an exothermic reaction, and the film formation rate is significantly higher than that of H2 reduction, which is an endothermic reaction. As a result, the inside of the contact hole 13 was uniformly filled with the second selective W layer 17, and the plug portion 18 was completed.

Example 3 This example is an example in which the first conductive material layer and the second conductive material layer constituting the plug portion are both made of W and are formed by a single step selective CVD method. It is. This process will be explained with reference to FIGS. 7(a) to (d). However, in FIG. 7, parts common to those in FIG. 6 will be described using the same numbers.

FIG. 7(a) shows Al-1% lower layer wiring.
A connection hole 13 is opened in the interlayer insulating film 12 on the Si layer 11, and a film-like re-deposition 14 and a particulate re-deposition 15 originating from the Al-1%Si layer 11 are formed on the side wall of the connection hole 13. The state of the wafer is shown in which a wafer is formed.

The above wafer was set in a parallel plate type plasma etching apparatus, and a Cl2 flow rate of 30S was set as an example.
The surface layer portion of the Al-1%Si layer 11 was isotropically etched under the conditions of CCM, gas pressure of 80 Pa (0.6 Torr), and RF power density of 0.2 W/cm 2 (13.56 MHz). As a result of this etching, as shown in FIG. 7(b), a recess 13a was formed at the bottom of the connection hole 13, and the redeposited substances 14 and 15 were removed. However, a small amount of AlCl3 19, which is an etching reaction product with a low vapor pressure, remains on the surface of the recess 13a, and if left as it is, there is a risk that it will cause uneven growth of W in the subsequent process. .

Therefore, the wafer was transferred to a CVD apparatus and first heated to 300 to 400° C. to volatilize and remove AlCl3 19 as shown in FIG. 7(c). After that, as an example, WF6 flow rate 10SCCM, SiH4 flow rate 7SC
CM, H2 flow rate 1000SCCM, gas pressure 27Pa (
Selected CV under the conditions of 0.2Torr) and substrate temperature of 260℃
I did D. In this example, redeposit 14, 15 and A
Since the lCl3 19 has been removed in advance, the recess 13a
The contact hole 13 was buried almost flat with the selective W layer 20 to form a plug portion.

Although the present invention has been described above based on three embodiments, the present invention is not limited to these embodiments. For example, the present invention is not limited to these embodiments. may be made of different types of metals. Furthermore, the processes performed in each of the above embodiments may be combined as appropriate. For example, after isotropically etching the lower wiring layer, the wafer is heated to volatilize and remove reaction products with low vapor pressure, and H2 reduction is performed. Selection CVD using
It is also possible to fill the recesses with the first conductive material layer by a method and then fill the connection holes by a blanket CVD method.

[0029]

[Effects of the Invention] As is clear from the above explanation, by applying the present invention, by isotropically etching a part of the lower wiring layer prior to selective growth of the conductor material layer, the sidewall of the connection hole can be improved. It becomes possible to remove redeposit existing in the area and perform uniform selective growth. Moreover, due to the shape effect of the recessed portion, the adhesion of the conductive material layer that becomes the plug portion is improved, and there is no need to provide a separate adhesion layer as in the conventional case. In addition, when the conductive material layer filling the connection holes is formed particularly by blanket CVD, connection holes of different depths can be satisfactorily filled without worrying about failure of selectivity during film formation. Furthermore, even if all connecting holes are filled by selective CVD, the process stability will be lower than before because reaction by-products and redeposit that cause abnormal nuclear growth have been removed in advance. Significantly improved. Therefore, the present invention is extremely useful for manufacturing semiconductor devices designed based on fine design rules and having high integration and high performance.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which contact holes with different depths are opened on an Al-1%Si layer having a step and re-deposition is formed in an embodiment of the wiring forming method of the present invention. It is.

FIG. 2: Al-1%Si in the wafer shown in FIG.
FIG. 4 is a schematic cross-sectional view showing a state in which recesses are formed by isotropic etching of the layer and redeposited matter is removed.

FIG. 3 is a schematic cross-sectional view showing a state in which the recess shown in FIG. 2 is filled with a selective W layer by a selective CVD method.

[Fig. 4] Blanket C is applied to the entire surface of the wafer shown in Fig. 3.
FIG. 2 is a schematic cross-sectional view showing a state in which a blanket W layer is formed by a VD method.

5 is a schematic cross-sectional view showing a state in which the entire surface of the wafer shown in FIG. 4 is etched back, leaving a blanket W layer only inside the contact hole and forming a plug portion; FIG.

FIG. 6 is a schematic cross-sectional view showing another embodiment of the wiring forming method of the present invention according to the process order, and (a) is an Al-
A connection hole is opened in the interlayer insulating film on the 1% Si layer and re-deposited matter is formed. (b) is a state in which a recess is formed in the Al-1% Si layer by isotropic etching and the re-deposited matter is removed. (c) shows a state where the recess is filled with the first selected W layer, and (d) shows a state where the connection hole is filled with the second selected W layer.

FIG. 7 is a schematic cross-sectional view showing still another embodiment of the wiring forming method of the present invention according to the process order, in which (a) a contact hole is opened in an interlayer insulating film on an Al-1% Si layer;
(b) is a state in which re-deposit is formed, (c) is a state in which a recess is formed by isotropic etching of the Al-1%Si layer, (c)
) represents a state in which residual AlCl3 has been volatilized and removed from the surface of the recess, and (d) represents a state in which the recess and the connection hole are filled with the selected W layer.

FIG. 8 is a schematic cross-sectional view for explaining the problems of the conventional wiring forming method, in which (a) shows a state in which re-deposited substances are formed inside the connection hole, and (b) shows a state in which redeposit is formed inside the connection hole. Each figure represents a state in which the W layer has grown non-uniformly.

FIG. 9 is a schematic cross-sectional view illustrating a problem when connection holes of different depths are filled by selective CVD in a conventional wiring forming method.

[Explanation of symbols]

1,11...Al-1%Si layer 2,12...Interlayer insulating film 3
...first connection hole 4
...Second connection hole 3
a, 4a, 13a... recess

Claims (1)

[Claims] 1. A wiring forming method in which a contact hole opened in an insulating film on a lower wiring layer is filled with a conductive material layer, wherein a part of the lower wiring layer in the layer thickness direction is isotropically filled through the contact hole. a step of forming a recess with an opening end larger than a peripheral edge of the contact hole by selectively etching the contact hole; a step of selectively growing a first conductive material layer at least in the recess; and filling with a second conductive material layer.