JPH0431329B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive converter that converts a physical quantity such as displacement into an electrical signal via capacitance, and particularly relates to a capacitive converter that converts a physical quantity such as displacement into an electrical signal via capacitance, and particularly relates to a capacitive converter that converts a physical quantity such as displacement into an electrical signal via capacitance. This article relates to a capacitive converter that eliminates effects and improves environmental resistance.

<Prior Art> Various types of capacitive transducers have been proposed that detect displacement and the like as changes in capacitance. Among these, a conventional capacitive converter, which is the basis for the improvement of the present invention, is shown in FIG. 4 and will be described.

C ₁ and C ₂ are sensor capacitances whose capacitance values change differentially depending on displacement or the like. One end of each of the sensor capacitors C ₁ and ₂ is connected, and further connected to the input end of the buffer gate G ₁ . The output end of buffer gate G ₁ is connected to inverter G ₂ and bidirectional constant current circuit CC
Negative feedback is connected to the input terminal of buffer gate _G1 through.

The output end of inverter _G2 is the input end of counter CT
CL, and its n-bit output terminal _Qo is connected to one end of the input of a NAND gate _G3 . The other input end of NAND gate _G3 is connected to the output end of inverter _G2 . The output end of NAND gate _G3 is connected to the other end of sensor capacitor _C1 .

On the other hand, the inverted output terminal _o of the counter CT is connected to one end of the input of the NAND gate _G4 , and the other end is connected to the output terminal of the inverter _G2 . The output end of NAND gate _G4 is connected to the other end of sensor capacitor _C2 .

Further, the output terminal Q _o of the counter CT is connected to the input terminal of the duty-to-analog converter DA, and a variable voltage V is obtained at the output terminal thereof.

Note that a capacitor is installed between the output terminal of inverter G ₂ and the input terminal of buffer gate G ₁ to remove the fixed capacitance included in sensor capacitances C ₁ and C ₂ .
C ₃ is connected.

Buffer gate G ₁ , inverter G ₂ , NAND gates G ₃ , G ₄ , counter CT and duty/analog converter DA all have positive power supply +E and negative power supply –
It is energized by E. In addition, Batsufua Gate G ₁
The inverter _G2 is constructed of C-MOS, for example, as shown in FIG.

The operation of the capacitive conversion device configured as described above will be explained using the waveform diagram shown in FIG. 6.

When the output terminal Q _o of the counter CT becomes high level "H" (Fig. 6 b), the output level of the inverter G ₂ , for example -E, is applied to the input terminal of the buffer gate G ₁ via the NAND gate G ₃ and the sensor capacitor C ₁ . Positive feedback will be given. As a result, as shown in Figure 6A, the voltage at the input terminal of the buffer gate _G1 becomes larger than the threshold value _VTH by _e1 , but in this case, the constant value constant current circuit CC
Since the discharge starts at a more constant current value i, the potential at the input end of the buffer gate _G1 decreases linearly.
When the threshold value V _TH is reached, the output of the buffer gate G ₁ is inverted, and the output level +E of the inverter _{G 2} is then positively fed back to the input terminal of the buffer gate G ₁ via the NAND gate G 3 and the sensor capacitor C ₁ , and its potential becomes the threshold value. It becomes smaller than V _TH by e′ ₁ (=-e ₁ ) (Fig. 6 A), but in this case as well, the bidirectional current circuit CC starts discharging in the opposite direction at a constant current value i, so the buffer gate is linearly The potential at the input terminal of _G1 increases. When the threshold value V _TH is reached, the output of the buffer gate G ₁ is inverted and returns to the initial state. Each time the above operation is repeated, the count value of counter CT increases,
When the predetermined number of bits n is counted, the level of the output terminal _Qo of the counter CT is reversed and _o becomes " _H " level, and the sensor
Oscillation on the _C2 side continues. In this case, the potential fluctuation at the input terminal of buffer gate G ₁ is e ₂ (=-e′ ₂ )
becomes.

In the above operation, the potential fluctuation at the sensor capacitor C ₁ and the capacitor C ₃ is 2E, so when the amount of charge fluctuation is taken into account, the following equation holds true.

e ₁ = C ₁ − C ₃ / C ₁ + C ₂ + C ₃・2E (1) Perform the same calculation on the sensor capacitance C ₂ side, e ₂ = C ₂ − C ₃ / C ₁ + C ₂ + C ₃・2E (2) becomes. Discharge time t ₁ (=t′ ₁ ), t ₂ on sensor C ₁ side and C ₂ side due to discharge in bidirectional constant current circuit CC
(=t' ₂ ) is expressed by the following equation, taking into account that the discharge is at a constant current value i.

t ₁ = (C ₁ + C ₂ + C ₃ ) e ₁ /i (3) t ₂ = (C ₁ + C ₂ + C ₃ ) e ₂ / i (4) On the other hand, the variable voltage V is the high level period of the output of the counter CT. It is given as an average voltage considering T ₁ and low level period T ₂ , but since high level period T ₁ and low level period T ₂ are multiples of discharge time t ₁ t ₂ , the following equation is obtained. To establish.

V=t ₁ −t ₂ /t ₁ +t ₂ E (5) Using equations (1) to (4), V=C ₁ −C ₂ /C ₁ +C ₂ −2C ₃ (6). By the way, the sensor capacitances C ₁ and C ₂ have capacitance components C' ₁ and C' ₂ that change due to displacement etc. and a capacitance component C _p that does not change, and the composite value of these is C ₁ = C' ₁
+C _p , C ₂ = C′ ₂ +C _p , so by substituting these into equation (6), V=C′ ₁ −C′ ₂ /C′ ₁ +C′ ₂ +2(C _p −C ₃ )(7
), a variable voltage V is obtained. Therefore, by taking capacitor C ₃ equal to C _p , the variable voltage V
is obtained in the form of a difference in the sum of sensor capacitances.

<Problems to be Solved by the Invention> However, in such a capacitive conversion device, since stray capacitance exists at both ends of the bidirectional constant current circuit CC, it has the same effect as the capacitor _C3 . Therefore, if this stray capacitance changes due to ambient temperature or the like, capacitors _C3 and _Cp may not cancel each other out well.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides first and second sensor capacitances that change according to physical quantities, and a connection with one end of each of the first and second sensor capacitances. gate means for changing the output level in response to a change in voltage exceeding a predetermined threshold; negative feedback means for supplying an inverted current from its output to the input of the gate; and negative feedback means for supplying an inverted current from its output to the input of the gate; an oscillation circuit having a first fixed capacitor for positive feedback of the common mode voltage from the oscillation circuit, a counting means for counting the change period of the output of the oscillation circuit, and changing the output voltage in response to the output level of the counting means. and a first excitation device that negatively feeds back the first excitation voltage to the input end of the gate device via the first sensor capacitor in accordance with the output level of the oscillation circuit during the first period when the voltage variable device has the first output level of the counting device. a second period through a second sensor capacitor depending on the output level of the oscillation circuit during a second period having a second output level of the counting means;
a second circuit for negatively feeding back the excitation voltage to the input terminal of the gate means;
an excitation gate, and a third excitation gate that feeds back a third excitation voltage to the input end of the gate means via a second fixed capacitor according to the output level of the oscillation circuit, and The gate outputs the voltage of the voltage variable means as one of the first, second, and third excitation voltages, and is configured to control the first period and the second period to be equal.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Note that parts having the same functions as those in the prior art are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

A capacitor _C4 is connected as a first fixed capacitor to the input and output terminals of the buffer gate _G1 for positive feedback. On the other hand, a bidirectional constant current circuit CC is connected between the output terminal of inverter G ₂ connected to the output terminal of buffer gate G ₁ and the input terminal of buffer gate G ₁ .
has been connected and negative feedback has been made. These buffer gate G ₁ , inverter G ₂ , capacitor C ₄ and bidirectional constant current circuit CC constitute an unstable oscillation circuit.

Further, G ₃ is a NAND gate that functions as a first excitation gate, and G ₄ is a NAND gate that functions as a second excitation gate. Both the negative power terminal of NAND gate G ₃ and the positive power terminal of NAND gate G ₄ are connected with a variable voltage V. Forced. One ends of the inputs of the NAND gates _G3 and _G4 are connected to the output terminal _Qo and the inverted output terminal _o of the counter CT, respectively, and their other ends are both connected to the output terminal of the buffer gate _G1 .

C ₃ is a capacitor as a second fixed capacitor for removing the capacitance component C _p of the sensor capacitances C ₁ and C ₂ ;
One end thereof is connected to the input end of buffer gate _G1 , and the other end is connected to the output end of NAND gate _G5 functioning as a third excitation gate.

One end of the input of the NAND gate _G5 is connected to the output end of the inverter _G2 , and the other end of the input is connected to the inverted output end _o of the counter CT. Zero voltage is applied to each end.

Note that it is assumed that a stray capacitance C _S exists at both ends of the bidirectional constant current circuit CC.

Next, the operation of the embodiment shown in FIG. 1 constructed as above will be explained.

During the period T _1A in which the level of the output terminal Q _o of the counter CT is "H" level, the NAND gate G ₃ and the sensor capacitance
Negative feedback is applied to the input terminal of buffer gate _G1 via _C1 . During the period _T2A when the output terminal _Qo of the counter CT is at the "L" level, _o is at the "H" level,
Negative feedback is applied to the input terminal of buffer gate _G1 via NAND gate _G4 and sensor capacitor _C2 , and positive feedback is applied via NAND gate _G5 and capacitor _C3 .
In this case, if the relationship is C ₁ < (C ₂ − C ₃ ), the voltage change at the input terminal of buffer gate G ₁ when switching to the sensor capacitance C ₁ side is _1A and the sensor capacitance switching to the C ₂ side. The relationship with the voltage change e _2A at the input terminal of the buffer gate G ₁ when the voltage is applied is e _1A > e _2A , and the relationship between the periods T _1A and T _2A is T _1A > T _2A . Therefore, in this case, the waveform corresponds to the operating waveform shown in FIG.

In the above operation, the potential fluctuation at sensor capacitor _C1 is (E-V), the potential fluctuation at sensor capacitor _C2 is (E+V), (V-O) at capacitor _C3 , 2E at capacitor _C4 , and the stray capacitance. Since there are potential fluctuations of -2E in _Cs , the following equation can be obtained by considering the charge fluctuations due to these potential fluctuations.

e _1A = 2EC ₄ -(E-V)C ₁ +2EC _s /C ₁ +C ₂ +C ₃ +C ₄ +C _s (8) e _2A = 2EC ₄ -(E+V)C ₂ +(V-O)C ₃ -2EC _s ／ _C1 ＋ _C2 ＋
C ₃ +C ₄ +C _s (9) Also, the discharge period t _1A corresponding to the sensor capacitance C ₁ ,
_The discharge _period t _2A corresponding to _the sensor _{capacitance C 2} is _calculated as in the case _{of FIG} . ₁ +C ₂ +C ₃ +C ₄ +C _s )e _2A /i (11).

In the case of T _1A > T _2A , the variable voltage V which is the output of the duty analog converter DA in Fig. 1
is in a decreasing state, thus leading to a decrease in e _1A in equation (8). In this way, T _1A = T _2A (t _1A = t _2A )
Then, from equations (10) and (11), e _1A = e _2A , so (8), (9)
From the formula, 2E( _C4 + _Cs )-(E-V) _C1 =2E( _C4 + _Cs )-(V+E) _C2 +(V-O) _C3 (12). Here, using the relationships C ₁ = C' ₁ + C _p and C ₂ = C' ₂ + C _p , and further selecting C ₃ = 2C _p , V = C' ₁ - C' ₂ /C' ₁ + C' ₂ E (13) is obtained.

This formula also applies to the capacitance component C _p of sensor capacitance C ₁ and C ₂ ,
This shows that it is not affected by the stray capacitance C _s at both ends of the bidirectional constant current circuit CC. Moreover, the capacity component
Since C _p is erased by selecting C ₃ =2C _p and is erased independently of the stray capacitance C _s , the conventional problem is solved.

FIG. 2 shows a NAND gate G in which one of the input terminals of the NAND gate _G5 , which functions as the _third excitation gate in the _embodiment shown in FIG. A modified embodiment configured as _{No. 6} is shown.

In this case, what is the voltage change e 1B at the input end of buffer gate _{G 1 when} the sensor capacitance C is switched to _{the 1 side} and the voltage change e _2B at the input end of the buffer gate G ₁ when the sensor capacitance C is switched to _{the 2} side? , Equations (8), (9)
In the same way as when deriving , it is expressed by the following equation.

e _1B = 2EC ₄ −(E−V)C ₁ −(V−O)C ₃ −2EC _s /C ₁ +C ₂ +
C ₃ +C ₄ +C ₅ (14) e _2B = 2EC ₄ - (E + V) C _{2 -} 2EC _s /C ₁ +C ₂ +C ₃ +C ₄ +C ₅ (15) In this case as well, follow the same procedure as in Fig. 1. The same result as equation (13) is reached.

Note that by adding the configuration shown in Figure 2 to the configuration shown in Figure 1, creating two second fixed capacitors _C3 and applying the output of the NAND gate _G6 to one of them, Even if we choose equal to the capacitance component C _p ,
The same result as equation (13) is obtained.

The NAND gates G ₃ , G ₄ , G ₅ and the like constituting the first, second and third excitation gates are logic gates that are energized with arbitrary energizing voltages +E and -E, for example, as shown in FIG. Using analog switches SW ₁ and SW ₂ operated by the outputs of G ₇ and G ₈ , the required voltages such as +E and V are applied to the sensor capacitors C ₁ and C ₂ and capacitors.
It may be output by switching to _C3 as an excitation voltage.

Furthermore, when all the polarities of the outputs of the NAND gates G ₃ , G ₄ , and G ₅ forming the first, second, and third excitation gates are inverted, for example, when changing the NAND gate to an AND gate, the sensor capacitances C ₁ , C ₂ , The feedback mode occurring through capacitor C ₃ is reversed, but
Even in this case, equation (13) is reached. However, in this case, for example, the potential change e _1A will be a large value,
There is a possibility that an excessive input will be applied to the buffer gate _G1 .

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the capacitance component that does not respond to displacement included in the sensor capacitance and the negative feedback means included in the unstable oscillation circuit Since the structure separates stray capacitance and erases each other independently, even if stray capacitance fluctuates due to the influence of the environment, the capacitance component that does not respond to displacement can be reliably erased, and electricity based on the true changing component can be erased. I can get a signal.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a partial configuration diagram with a different connection configuration of the third excitation gate in Figure 1, Figure 3 is a circuit configuration diagram showing a modification of each excitation gate in Figure 1, and Figure 4 is a conventional capacitive converter. FIG. 5 is a partial configuration diagram showing the specific structure of the gate in FIG. 4, and FIG. 6 is a waveform diagram showing operating waveforms of each part in FIG. 4. C ₁ , C ₂ ... Sensor capacitance, G ₁ ... Buffer gate, G ₂ ... Inverter, G ₃ , G ₄ , G ₆ ... NAND gate, C _s ... Stray capacitance, CT ... Counter,
DA...Duty analog converter, CC...Bidirectional constant current circuit.

Claims (1)

[Claims] 1 first and second sensor capacitances that change according to physical quantities; and gate means that is connected to one end of each of the first and second sensor capacitances and changes an output level in response to a change in voltage that exceeds a predetermined threshold. an oscillation circuit having negative feedback means for supplying an inverted current to the input end of the gate means from its output end; and a first fixed capacitor for positive feedback of a common mode voltage from the output end to the input end of the gate means; a counting means for counting the change period of the output of the oscillation circuit; a voltage variable means for changing the output voltage in response to the output level of the counting means; The first
a first excitation gate that negatively feeds back an excitation voltage to the input end of the gate means; and a first excitation gate that negatively feeds back the excitation voltage to the input terminal of the gate means; a second excitation gate that negatively feeds back a second excitation voltage to the input end of the gate means; and a third excitation voltage that feeds back a third excitation voltage to the input end of the gate means via a second fixed capacitor depending on the output level of the oscillation circuit. a third excitation gate, the first, second and third excitation gates output the voltage of the voltage variable means as one of the first, second and third excitation voltages; A capacitive conversion device characterized in that the period and the second period are controlled to be equal.