JPH0431332B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Prior Art> FIG. 5 is a block diagram showing an example of a conventional capacitive converter. This type of capacitive converter is disclosed, for example, in Japanese Patent Laid-Open No. 10524/1983.

A bidirectional constant current circuit CC is connected between the input and output terminals of the NAND gate _G1 , and its output terminal is connected to one end of the variable capacitor _C1 to be detected via the NAND gate _G2 . The other end of variable capacitor _C1 is capacitance
It is connected to the common potential point COM via _C2 and to the input terminal of the NAND gate _G1 .

The bidirectional constant current circuit CC has field effect transistors Q ₁ and Q ₂ connected in series between their drains and sources, and resistors R ₁ and R ₂ generated by the current flowing through the resistors R ₁ and R ₂ . The terminal voltage is applied to the gate as negative feedback, forming a bidirectional constant current circuit.

Each element G ₁ and G ₂ is composed of CMOS and is powered by a positive power supply +E with respect to a common potential point COM.

Note that a distributed capacitance C _S is formed at both ends of the variable capacitance C ₁ , and a compensation capacitance C _cp that compensates for this distributed capacitance C _S
are connected to both ends of the bidirectional constant current circuit CC.

In the above configuration, for example, NAND gate G ₂
If we consider the case where the potential at the output terminal of G1 becomes high level (+E), the distributed capacitance _C1 is charged by this high level potential, the potential at the input terminal of NAND gate _G1 rises, and its threshold potential _VTH becomes When it exceeds this level, the output terminal inverts to low level. Since the input terminal of NAND gate G ₁ is at high level and the output terminal is at low level, bidirectional constant current circuit CC starts discharging with a constant current i, and after a predetermined time, reaches the threshold potential V _TH of NAND gate G ₁ . Therefore, the potential at the output terminal is inverted to high level.
In this case, the output terminal of NAND gate G ₂ is at low level, the input terminal of NAND gate G ₁ is at low level, and the output terminal is at high level, so that the variable capacitor C ₁ is charged by bidirectional constant current circuit CC. is started with a constant current i, and the potential at the input terminal of the NAND gate _G1 rises at a constant rate. When the potential at the input end of NAND gate _G1 reaches the threshold potential _VTH , its output end is inverted to low level and returns to the initial state. This is repeated to continue oscillation.

Since the bidirectional constant current circuit CC charges and discharges with a constant current i, the charging and discharging period is proportional to the value of the variable capacitor _C1 . Therefore, the value of variable capacitance C ₁ can be determined from the oscillation frequency at the output end of NAND gate G ₁ .

The distributed capacitance C _S at both ends of the variable capacitor C ₁ is the compensation capacitance C _cp
By selecting the same capacitance value as , compensation charge for the distributed capacitance C _S is performed by the compensation capacitance C _cp in the charged state, so that the influence of the distributed capacitance C _S on the output is eliminated.

<Problems to be Solved by the Invention> However, in the conventional capacitive converter shown in FIG. 5, the configuration of the bidirectional constant current circuit CC is complicated.
Moreover, even if the influence of the distributed capacitance C _S is compensated for by the compensation capacitance C _cp , since semiconductor elements such as transistors Q ₁ and Q ₂ are used, their junction capacitance changes when the temperature or voltage changes. This is a factor that causes nonlinear or span fluctuations.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a variable capacitor whose capacitance changes depending on the physical quantity to be detected, and an inverting capacitor with one end of the capacitor connected to the non-inverting input terminal. An operational amplifier has a divided voltage between the voltage at the output end and a constant voltage applied to the input end, and the output of the operational amplifier is applied to the input end, and the voltage at the output end is varied by the inverted phase of that voltage via a logic element. An inverter that applies voltage to the other end of the capacitor, and a resistor that is connected to the non-inverting input end of the operational amplifier from a voltage division point between the output of the operational amplifier and the output of the inverter. be.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

Resistors R ₃ and R ₄ are connected between the non-inverting input terminal (+) and the output terminal of the operational amplifier Q ₃ , and the inverting input terminal (-) resistors the constant voltage V ₀ and the voltage at the output terminal. A voltage divided by R ₅ and R ₆ is applied.

The output terminal of operational amplifier Q ₃ is connected to the input terminal of inverter G ₃ , and its output terminal is connected to the connection point of resistors R ₃ and R ₄ via resistor R ₇ , and the output terminal is connected to the variable capacitor via inverter G ₄ . Connected to one end of _C1 . The other end of variable capacitor C ₁ is connected to common potential point COM via capacitor C ₂ and operational amplifier Q ₃
is connected to the non-inverting input terminal (+) of

Note that operational amplifier Q ₃ and inverters G ₃ and G ₄ are energized with positive voltage +E, and inverters G ₃ and G ₄ are
Consists of CMOS transistors.

Next, the operation of the embodiment shown in FIG. 1 constructed as above will be explained using the waveform diagram shown in FIG. 2.

When the voltage _V4 at the output end of the inverter _G3 is at the high level shown in Figure 2D, the inverter
The output of G ₄ is low level, and variable capacitor C ₁ and capacitor C ₂ are charged through resistor R ₄ , and the operational amplifier
The potential at the input terminal of _Q1 rises as shown in period _T1 in FIG. 2A. Along with this, the voltage V ₃ at the output end of the operational amplifier Q ₃ (FIG. 2 C) and the voltage V ₂ at the connection point between the resistors R ₃ and R ₄ (FIG. 2 B) also rise. When voltage _V3 exceeds the threshold voltage _VTH of inverter _G3 , the level at its output terminal is inverted to low level. Therefore, the output terminal of inverter G ₄ becomes high level, and the voltage divided by variable capacitance C ₁ and capacitance C ₂ is applied to the non-inverting input terminal (+) of operational amplifier Q ₃ , and the voltage V ₁ rises vertically (Figure 2 A).
After that, since the output terminal of inverter G ₃ is at low level, variable capacitance C ₁ and electrostatic capacitance C ₂ are connected via resistor ₄ .
The charge continues to discharge during the period T ₂ shown in Figure 2 A,
The potential at the non-inverting input terminal (+) of operational amplifier _Q3 decreases. When the threshold voltage _VTH at the input end of inverter _G3 is reached, its output end is inverted to high level and returns to its original state. Therefore, the current flowing through the resistor R ₄ is a constant current i _c in the forward and reverse directions in response to the level change of the voltage V ₄ at the output terminal of the inverter G ₃ , similar to the bidirectional constant current circuit CC shown in FIG. Become. Therefore, oscillation as shown in FIG. 2 continues.

A quantitative explanation of the above points is as follows.
Voltages V ₁ to V ₄ satisfy the following relationship.

V ₄ −V ₂ /R ₇ =V ₂ −V ₁ /R ₄ +V ₂ −V ₃ /R ₃ (1) V ₃ = (1+R ₆ /R ₅ )V ₁ −R ₆ /R ₅ V ₀ (2 ) From the relationship of equations (1) and (2), V ₂ = R ₀ /R ₇ V ₄ −R ₀ /R ₃・R ₆ /R ₅ V ₀ + (1/R ₄ +1/R ₃ +R ₆ /R ₃ R ₅ ) R ₀ V ₁ (3). However, R ₀ =1/R ₇ +1/R ₃ +1/R ₄ .

Here, if R ₇ /R ₃ =R ₅ /R ₆ is selected, V ₂ −V ₁ =R ₀ /R ₇ (V ₄ −V ₀ ) (4). Here, if the constant voltage V ₀ is determined so that V ₀ =E/2, then V ₂ −V ₁ =R ₀ /R ₇ (V ₄ −E/2) (4)′. Therefore, since the voltage V ₄ repeats the two-level change of +E←→zero, the current i _c flowing through the resistor R ₄
is a constant current flowing in both directions with a magnitude of i _c =|V ₂ −V ₁ |/R ₄ =R ₀ /R ₄ R ₇ |E/2| (5).

Note that in order to prevent oscillation in the operational amplifier _Q3 , the amount _of positive feedback is reduced by selecting _R4≫R6 .

Next, when considering the charge fluctuation in the variable capacitor _C1 , the following equation holds true.

T ₁ ·i _c =C ₁ E (6) Therefore, the period T ₁ is obtained as T ₁ =C ₁ /i _c E (6)′, and the same is true for the period T ₂ . Therefore, the frequency at the output end of inverter _G3 has a value proportional to variable capacitance _C1 .

Note that the distributed capacitance C _S at both ends of the variable capacitor C ₁ is a resistance
Compensation is performed by the compensation capacitor C′ _cp connected to both ends of R _4. In this case, since the compensation capacitor is connected to both ends of resistor R ₄ , the influence of the junction capacitance of the semiconductor element is eliminated as in the conventional case. I don't accept it.

FIG. 3 is a block diagram showing an embodiment in which a differentially varying capacitor is used as the variable capacitor.
Components having the same functions as those in the embodiment shown in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted as appropriate.

The output end of inverter _G3 is NAND gate _G5 , _G6
Its output terminals are connected to one terminal of each of the differential capacitances C _L and C _H as well as to each input terminal of the NAND gate G ₇ . The output end of NAND gate _G7 is connected to one end of resistor _R7 .

The other ends of the differential capacitors C _L and C _H are both capacitors C ₂
It is connected to the common potential point COM via the COM and to the non-inverting input terminal (+) of the operational amplifier _Q3 .

The output terminal of inverter _G3 is connected to the input terminal CL of n-bit counter CT via inverter _G8 , and its output terminal _Qo is connected to the other input terminal of NAND gate _G6 and via inverter _G9 . and is connected to the other input terminal of NAND gate _G5 . Obtain the output V _put from the output terminal of inverter _G9 .

Next, the operation of the embodiment shown in FIG. 3 constructed as above will be explained using the waveform diagram shown in FIG. 4.

First, when the output terminal _Qo of the counter CT is at a low level, _G5 is selected from among the NAND gates _G5 and _G6 , and the output terminal of _G6 is kept at a high level. Therefore, since NAND gates G ₅ and G ₇ each function as a simple inverter, NAND gate G ₅
has the same function as inverter _G4 in Figure 1, and the output terminal of NAND gate _G7 is connected to inverter _G3.
The level change is the same as that at the output terminal.

Therefore, when the output terminal Q _o of the counter CT is at a low level, that is, during the period T _L shown in FIG. 4 _, the operation is the same as when the variable capacitor C ₁ in FIG. Therefore, the voltage at the input terminal of operational amplifier Q ₃ is V ₁ ′, and the voltage at the connection point of resistors R ₃ , R ₄ , and R ₇
V ₂ ′, the voltage V ₃ ′ at the output end of the operational amplifier Q ₃ , and the voltage V ₄ ′ at the output end of the NAND gate G ₇ have the same waveforms as shown in FIG. 2, as shown in FIGS. 4A to 4D. This waveform is repeated by the number n of bits of the counter CT. Therefore, in the same way as formula (6)' was derived, the period T _L is determined by the following formula.

T _L =nC _L /i _c ′E (7) However, i _c ′ is i _c ′=R ₀ /R ₄ R ₇ |V ₄ ′−V ₀ |.

When the counter CT counts n pulses related to the differential capacitance _CL , the level of its output terminal _Qo is inverted to high level. In this state, Nand Gate
Among _G5 and _G6 , _G6 is selected, and the output terminal of _G5 is kept at a high level. Therefore, Nand Gate G ₅ ,
Each G ₇ acts as just an inverter,
NAND gate G ₆ is inverter G ₄ in Fig. 1
It has the same function as . Also, Nand Gate G ₇
The output terminal of inverter _G7 has the same level change as the output terminal of inverter G7.

Therefore, when the output terminal Q _o of the counter CT is at a high level, that is, during the period T _H in FIG. 4, _the operation is the same as when the variable capacitor C ₁ in FIG. Similarly to the period T _L ,
The period T _H is T _H =nC _H / _ic ′E (8).

Therefore, the output _Vput has a period as shown in Fig. 4E.
A pulse waveform repeats T _L and T _H , and when these are averaged, a value proportional to the displacement of the common electrode forming the differential capacitances C _L and C _H is obtained.

Note that the distributed capacitances C _{SL and} C _SH formed at both ends of the differential capacitances C _L and C _H are almost the same due to their configuration, so they are equal to the compensation capacitance C _cp ″ connected to both ends of the resistor _R4 . The points that can be removed by selection are the same as in the embodiment shown in FIG.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, the bidirectional constant current circuit is not constructed using semiconductors as in the past, so distributed capacitance such as temperature or voltage can be reduced. It is possible to realize a stable capacitive converter that is not affected by fluctuations in .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a waveform diagram showing the waveforms of each part of the embodiment shown in FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a waveform diagram of each part of the embodiment shown in FIG. FIG. 5 is a waveform diagram showing waveforms, and a block diagram showing the configuration of a conventional capacitive converter. C ₁ ... Variable capacitance, C _L , C _H ... Differential capacitance, CC...
...Bidirectional constant current circuit, C _S , C _SL , C _SH ... Distributed capacitance, C _cp , C _cp ′ ... Compensation capacitance, CT ... Counter.

Claims (1)

[Claims] 1 A variable capacitor whose capacitance changes according to the physical quantity to be detected, and an operational amplifier in which one end of the capacitor is connected to the non-inverting input terminal and a divided voltage of the output terminal voltage and a constant voltage is applied to the inverting input terminal. an inverter having an input terminal to which the output of the operational amplifier is applied, and applying a voltage at the output terminal to the other terminal of the variable capacitor in an inverted phase of the voltage through a logic element; A capacitive converter comprising: a resistor connected to a non-inverting input terminal of the operational amplifier from a voltage dividing point with an output.