JPH0431330B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive differential pressure transmitter that converts differential pressure, etc. into an electrical signal via capacitance, and in particular, relates to a capacitive differential pressure transmitter that converts differential pressure etc. into an electrical signal via capacitance, and in particular, transmits a digital signal to the outside. This article relates to capacitive differential pressure transmitters that can be used.

<Prior art> Conventional differential pressure transmitters are constructed using capacitive sensors or strain gauges, and most have four to four
It has been configured to convert it into a unified analog signal such as 20mA and transmit it to a distant receiver over a two-wire line, for example.

Therefore, these differential pressure transmitters have been constructed mainly using analog calculation circuits.

<Problems to be Solved by the Invention> Since conventional differential pressure transmitters were mainly configured with an analog calculation circuit, there was a drawback that the performance of the entire differential pressure transmitter was determined by the performance of this analog calculation circuit. .

<Means for solving the problem> Therefore, in the present invention, a capacitive sensor is interfaced to a digital calculation section using, for example, a C-MOS logic device, without using an analog calculation circuit such as an operational amplifier. This provides a method for transmitting signals with high accuracy. Therefore, in the present invention, first and second sensor capacitances that change according to the differential pressure, a fixed capacitor having one end connected to a common connection point to which one end of each of the sensor capacitances is connected, and this common connection point a detection gate means having an input terminal connected to the input terminal and changing an output level in response to a change in the input voltage exceeding a predetermined threshold and negatively feeding back the change in the output level to the input terminal, and a change in the output level of the detection gate means. A counting means for counting cycles, and a first fixed voltage and a variable voltage are alternately applied to the other end of the first sensor capacitor in response to the output level of an arbitrary bit of the counting means and the output level of the detection gate means. a first excitation means; a second excitation for alternately applying a variable voltage and a second fixed voltage to the other end of the second sensor capacitor in response to the output level of an arbitrary bit of the counting means and the output level of the detection gate means; a third gate means for alternately applying a variable voltage and a reference voltage to the other end of the third fixed capacitor in response to at least the output level of the detection gate means;
An operation signal comprising an excitation gate means and a microcomputer, which reads the difference in retention time of each level of the two-position signal generated in the output of the counting means, and raises or lowers the variable voltage according to the polarity of this time difference. The apparatus is configured to include a digital calculation means having a communication means for outputting a transmission signal and further transmitting a transmission digital signal related to the operation signal to the outside.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. 10 is an interface section, and 20 is a digital calculation section.

One end of each of the sensor capacitors C ₁ and C ₂ is connected to the input end of an inverter G ₁ that constitutes a detection gate.
There is a resistor R _c between the input and output ends of the inverter _G1 .
A negative feedback is connected.

The output end of inverter _G1 is an n-bit counter.
It is connected to the input end CL of CT ₁ A, and its output end Q _o is connected to one end of the input of AND gate G ₂ serving as the first excitation gate means. Further, the output terminal Q _o is connected via an inverter G ₃ to one end of the input of an AND gate G ₄ serving as a second excitation gate means. The other input ends of AND gates G ₂ and G ₄ are connected to the output end of inverter G ₁ via inverter G ₅ .

The buffer gate _G6 receives the operation signal _Dpp from the digital calculation section 20, and outputs a pulse signal whose duty ratio changes to its output terminal. This pulse signal is converted into a variable voltage V by a filter composed of a resistor R ₁ and a capacitor C ₄ .

The positive power supply terminal of the inverter _G7 serving as the third excitation gate is connected to a variable voltage V, the negative power supply terminal is connected to a reference potential point C, and the inverter G7 is connected to its input terminal.
The voltage at the output end of _G1 is applied. The output of the inverter _G7 is connected to the other end of a capacitor _C3 , one end of which is connected to the input of the inverter _G1 .

A positive voltage +E and a variable voltage V are applied to the positive power terminal and negative power terminal of AND gate G ₂ , respectively, and a variable voltage V and a negative voltage -E are applied to the positive power terminal and negative power terminal of AND gate G ₄ , respectively. is being applied.

The output end of the counter CT ₁ is connected to one end of the input of an exclusive sieve-or gate G ₈ as a monitoring gate. Exclusive Thiev or Gate
A detection signal D _s from the digital calculation unit 20 is applied to the other input end of G ₈ .

CT ₂ is a clock counter whose input terminal CL
Then, it receives a clock pulse P _c from the digital calculation unit 20, simply counts it, encodes time information, and outputs it from the output terminal Q to the digital calculation unit 20 as a digital signal D _c of required bits.

Of the above configuration, the portion excluding the sensor capacitors C ₁ and C ₂ and the capacitor C ₃ constitutes an interface unit 10 to the digital calculation unit.

Of the digital calculation unit 20, RAM is random access memory, ROM is read-only memory,
CPU is a microprocessor, IO ₁ is an input/output port for signal transmission, TC is a transmission circuit for receiving the output of input/output port IO ₁ and transmitting current signals and other commonly used signals, IO ₂ , IO ₃ , IO ₄ are input/output ports connecting with the interface unit 10, and these elements are connected by a bus BS.

CLG is a clock generator that generates a clock pulse _Pc , and this clock pulse _Pc is sent to a clock counter _CT2 and a microprocessor CPU.
supply each.

The input/output port _IO2 applies a detection signal _Ds to the other input end of the exclusive sieve-or gate _G8 based on a command received from the microprocessor CPU via the bus BS. A digital signal D _c , which is time information in the clock counter CT ₂ , is stored in the input/output port IO ₃ by the trigger pulse P _T generated at the output terminal.

On the other hand, the signal processed by the microprocessor CPU is outputted to the buffer gate _G6 as an operation signal _Dpp via the input/output port _IO4 .

Note that logic elements such as inverters G ₁ , G ₃ , G ₅ and buffer gate G ₆ are energized with positive voltage +E and negative voltage -E, and these values are, for example, +2.5 volts, -2.5 volts, etc. do. Furthermore, the inverter
Logic elements such as G ₁ , G ₃ , G ₅ , G ₇ , buffer gate G ₆ , AND gates G ₂ and G ₅ are P channel MOS-
C- composed of FET and N-channel MOS-FET
It is convenient to use a MOS circuit because the energizing voltage value becomes the output level voltage value.

Next, the operation of the capacitive differential pressure transmitter shown in FIG. 1 constructed as above will be explained using the waveform diagram shown in FIG. 2.

The output of counter CT ₁ is shown in Fig. 2 during period T _1.
When the output of inverter _G5 is at the low level "L" at the high level "H" shown by
The output of G ₂ (Figure 2, 1, c) is in the "L" state,
The input voltage e _i at the input end of inverter G ₁ is shown in Figure 2 1.
The output level of the output terminal of the inverter _G1 is "H" as shown in Figure 2 ( ₁ ), (B).
Since it is in the state, the sensor capacitance _{C 1} ,
C ₂ and capacitor C ₃ are charged and their potentials gradually rise. When the voltage e _i reaches the threshold level V _TH of the inverter G ₁ , the output of the inverter G ₁ is inverted, and the voltage e _i at the input end of the inverter G ₁ becomes the second
The state will be as shown in _A1 of Figure 1, A. In this case, since the threshold level V _TH is energized with the voltages +E and -E, the output of the inverter G ₁ is inverted when V _TH =0. This voltage change e ₁ is expressed by the following equation, taking into account the charge fluctuation at the input end.

e ₁ = C ₁ (E-V) + C ₃ V/C ₁ + C ₂ + C ₃ (1) In these conditions, the output of inverter G ₃ is the inverted output of counter CT ₁ , Therefore, the output of the AND gate _G4 is fixed at the "L" state, and only the sensor capacitor _C1 side is switched.

In the transient state after switching from state A ₀ to A ₁ , the initial value is set to the threshold level as shown in equation (1).
The discharge time t ₁ until the voltage e _i decreases to V _TH is calculated as follows: t ₁ =−R _c (C ₁ +C ₂ +C ₃ )lnE/(e ₁ +E) (2).

After the discharge time t ₁ has elapsed, the output of the inverter G ₁ is reversed (FIG. 2, 1, b). Inverter immediately after inversion
The voltage change e ₁ ′ at the input terminal of G ₁ is the same as equation (1).
Therefore, the discharge time t ₁ ' in the reverse direction to the sensor capacitances C ₁ and C ₂ and the capacitor C ₃ in this case also has the value shown by equation (2). This discharge time is shown in Figure 2, 1, A.
This is the area indicated by A ₁ ′.

Next, the output of counter CT ₁ is shown in Fig. 2.
When the low level is "L" indicated by _T2 , the output of the AND gate _G2 is fixed to the "L" state, and the output of the AND gate _G4 changes according to the change in the output level of the inverter _G1 (second Figure 1, d). In this case, the operation related to charging and discharging of the sensor capacitances C ₁ and C ₂ and the capacitor C ₃ is the same as in the case of period T ₁ , and the change e ₂ of the input voltage e _i and the discharge time t ₂ are respectively expressed by the following formulas. The value shown will be the value shown.

e ₂ = C ₂ (E + V) - C ₃ V/C ₁ + C ₂ + C ₃ (3) t ₂ = - R _c (C ₁ + C ₂ + C ₃ )lnE/e ₂ + E (4) Output level of inverter G ₁ The voltage change e ₂ ′ in the opposite direction due to the change in is also the same value as e ₂ , and therefore the discharge time t ₁ ′ in the reverse direction is also the same value as the value shown in equation (4).

On the other hand, the digital calculation section 20 outputs the operation signal D _pp to the input terminal of the buffer gate G ₆ so that the periods T ₁ and T ₂ of the output pulses of the counter CT ₁ are equal, as will be described later. A pulse signal with the waveform shown in Fig. 2, 1, is outputted to its output terminal, and this is connected to the resistor R ₁ ,
A variable voltage V is obtained by smoothing with a filter consisting of a capacitor _C4 . Inverter with this variable voltage V
Since G ₇ is energized, the voltage applied to the other end of capacitor C ₃ (FIG. 2, 1, E) varies according to the magnitude of variable voltage V, and periods T ₁ and T ₂ are made equal.

The count values obtained by counting the number of changes at the input terminal of the counter CT ₁ corresponding to the discharge time t ₁ t ₂ by n bits are T ₁ and T ₂
Therefore, by making equations (2) and (4) equal, e ₁ =e ₂ can be obtained, and by making equations (1) and (3) equal, the following equation can be obtained.

C ₁ (E-V) + C ₃ V = C ₂ (E + V) - C ₃ V (5) Here, the sensor capacitances C ₁ and C ₂ are the change components C ₁ ′ and C ₂ ′ that change due to the differential pressure, and the floating It is expressed as the sum of the constant component C _p that does not change due to capacitance, etc., so if equation (5) is rewritten using these components, (C ₁ ′ + C _p ) (E-V) + C ₃ V = (C ₁ ′+C _p )(E+
V)+C ₃ V (6). If C ₃ and C _p are selected to be equal and the invariant component C _p is eliminated, equation (6) becomes the following equation (7).

V=C ₁ ′−C ₂ ′/C ₁ ′+C ₂ ′E (7) Therefore, the variable voltage V can be expressed only by the change components C ₁ ′ and C ₂ ′ where the capacitance changes due to the differential pressure. can. Further, since _the variable voltage V is a _voltage obtained by smoothing _the waveform _of FIG. From equations (7) and (8), C ₁ ′−C ₂ ′/C ₁ ′+C ₂ ′=T ₁₀ −T ₂₀ /T ₁₀ +T ₂₀ (9).

Therefore, the differential pressure can be determined from the values of T ₁₀ and T ₂₀ . The values of T ₁₀ and T ₂₀ are calculated by the digital calculation section 2.
Since the value is sent from 0, the corresponding signal can be transmitted from the input/output port IO ₁ via the transmission circuit TC, for example, as a digital signal.

Next, the operation centered on signal processing in the digital arithmetic unit 20 will be explained.

In the digital calculation unit 20, memory RAM or
The input/output port IO ₂ is controlled by the microprocessor CPU by the program written in the ROM.
The detection signal D _s with the waveform shown in FIG.
is output to the other end of the input of exclusive sieve-or gate _G8 . On the other hand, from the output terminal Q _o of the counter CT ₁ , an output signal having the waveform shown in FIG. 2, A is applied to one input terminal of the exclusive OR gate G ₈ .

When the detection signal D _s is in the “L” state, the trigger pulse P _T output from the exclusive sieve-or gate G ₈ is applied to the counter CT ₁ as shown in FIG.
The change in the output level from “L” to “H” is regarded as “H” level and input terminal T _r of input/output port IO ₃
transmitted to. Conversely, when the detection signal D _s is in the "H" state, the trigger pulse P _{T is} set to the "H" level when the output level of the counter CT ₁ changes from "H" to "L". It is transmitted to the input terminal T _r .

Clock counter CT ₂ is a clock generator
The clock pulse P _c (FIG. 2, d) of CLG is received at the input terminal CL, which is simply counted to encode time information and transmitted to the input/output port IO ₃ as a digital signal D _c of the required bits. D ₁ to D ₅ in FIG. 2 (e) are digital signals D _c modeled into 5 bits. This digital signal D _c is stored in the input/output port IO ₃ in synchronization with the rise of the trigger pulse _PT , and this storage state is the state Q ₁ to Q ₅ shown in FIG.

The microprocessor CPU generates time information at points TD ₁ to _{TD 5} following the inversion of the detection signal D _s .
Read Q ₁ to Q ₅ . In the example shown in Figure 2, F,
Zero at time TD ₁ , 10 at TD ₂ , 16 at TD ₃ , TD ₄
It is coded as 26 in TD ₅ and zero in TD 5.

Next, for example, in order to make _the time value read at time TD ₂ correspond to the length of TR ₁ , that is, _{T 1} shown in FIG _. Microprocessor CPU memory RAM or
The program stored in the ROM executes the following calculations.

Detection signal _Ds is "H" or YES: The content of data related to _T2 is updated.

NO: Update the data content regarding T ₁ .

Is the read value smaller than the previous value? YES: Update the data by (read value + 2 ^x ) - (previous value). x is the bit size, 5 in this example.

NO: Update data as (read value) - (previous value).

Update the previous value with the read value.

As a result of the calculation according to the above procedure, at time TD ₂ , T ₁ = (10 - 0) = 10 from the above read value, and at TD ₃ , T ₂ =
(16-10) = 6, in TD ₄ T ₁ = (26-16) = 10,
For TD ₅ we get T ₂ = (0 + 2 ⁵ - 26) = 6.

Based on these values of T ₁ and T ₂ , the microprocessor further performs the following operation to update the values of T ₁ and T ₂ .
Executed by CPU.

T ₁ > T ₂ or YES: Increase T ₁₀ and decrease T ₂₀ (Fig. 2, 1).

NO: Decrease T ₁₀ and increase T ₂₀ (Figure 2, 1).

By repeating the above calculation, the value of the variable voltage V can be changed from equation (8). Therefore, in the case of YES, the variable voltage V increases, so the voltage change e ₁ decreases and the voltage change e ₂ increases. If NO, the opposite change will occur. As a result, finally e ₁ = e ₂
Therefore, T ₁ = T ₂ .

Note that the microprocessor CPU inputs the trigger pulse _{P T} shown in FIG _. “L” to “H”, “H” to “L”
The microprocessor controls the generation of level changes to
Notify the CPU and read the input/output IO ₃ data.

In addition, although the bit configuration of the counter CT ₁ was explained as 2 bits in FIG. 2 and the clock counter CT ₂ as 5 bits, it is better to include a large number of clock pulses P _c in the time widths of T ₁ and T ₂ for better resolution. Preferable from above.

Furthermore, if the excitation current to the sensor capacitors C ₁ and C ₂ and the voltage drop in the filter are not small, a buffer amplifier with a gain of 1 may be interposed when sending out the variable voltage V from the smoothing circuit.

The excitation means is means for switching voltages such as +E, -E, and V according to logic signals, and C-
Any analog switch, not limited to MOS devices, can also be used.

The variable voltage V is the operating signal D _pp with a duty ratio.
However, the present invention is not limited to this, and means such as a D/A converter can also be used.

FIG. 3 is a block diagram showing another embodiment for obtaining the variable voltage V in FIG. 1. In this embodiment, instead of transmitting the duty cycle operation signal D _pp from the input/output port IO ₄ in FIG. 1, the input/output port IO ₅ is configured to simply transmit a code signal, and code/duty conversion is performed externally. This is to reduce the burden on the digital calculation section 21.

MC in Fig. 3 is a magnitude comparator, which receives the cyclic code from the clock counter CT ₂ and the code signal amplified by the input/output port IO ₅ at its input terminals DA and DB. The data are compared and transmitted to buffer gate _G4 as a duty cycle signal. In this case, equation (9)
The value of (T ₁₀ + T ₂₀ ) is determined by the bit size x of the digital signal D _c of the clock counter CT ₂ and is given by 2 ^x , and the value of T ₁₀ is given by the value of the code signal of the input/output port IO ₅ . It will be done.

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, differential pressure, etc. is converted into a change in capacitance, and this is input as a digital quantity to a microcomputer, and this digital value is The data is fed back to the first and second sensor capacitors as a variable voltage of an analog value to obtain a digital signal corresponding to the differential pressure. Therefore, the digital signal corresponding to this differential pressure can be transmitted directly as a digital value via the transmission circuit, and a highly accurate differential pressure transmitter can therefore be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a waveform diagram showing the waveforms of each part in Figure 1.
This figure is a block diagram showing another embodiment for obtaining variable voltage in FIG. 1. C ₁ , C ₂ ... Sensor capacity, G ₁ , G ₃ , G ₅ , G ₇ ...
Inverter, G ₆ ... Buffer gate, CT ₁ ...
Counter, CT ₂ ......Clock counter, IO ₁ ~
IO ₅ ...Input/output port, CPU...Microprocessor, BS...Bus, CLG...Clock generator, 10...Interface section, 20, 21...
…Digital calculation unit, V…Variable voltage, e _i …Input voltage, D _pp …Operation signal, P _c …Clock pulse,
P _T ...Trigger pulse, D _s ...Detection signal.

Claims (1)

[Claims] 1. First and second sensor capacitors that change according to the differential pressure, a fixed capacitor that has one end connected to a common connection point to which each end of the sensor capacitor is connected, and an input end that is connected to this common connection point. a detection gate means for changing the output level in response to a change in the input voltage exceeding a predetermined threshold and negatively feeding back the change in the output level to the input terminal; and a counter for counting the period of change in the output level of the detection gate means. and a first excitation for alternately applying a first fixed voltage and a variable voltage to the other end of the first sensor capacitor in response to the output level of an arbitrary bit of the counting means and the output level of the detection gate means. means, and a second means for alternately applying the variable voltage and the second fixed voltage to the other end of the second sensor capacitor in response to the output level of an arbitrary bit of the counting means and the output level of the detection gate means. an excitation gate means; a third excitation gate means for alternately applying the variable voltage and the reference voltage to the other end of the third fixed capacitor in response to at least the output level of the detection gate means; and a microcomputer. This microcomputer reads the difference in retention time of each level of the two-position signal generated in the output of the counting means, outputs an operation signal to raise or lower the variable voltage according to the polarity of this time difference, and further outputs this operation signal. 1. A capacitive differential pressure transmitter, comprising: a digital calculation means having a communication means for transmitting a transmission digital signal related to the transmission to the outside.