JPH04314150A - Main storage page control device - Google Patents

Abstract

PURPOSE:To realize transfer by the page unit of the page of the longest lapse of time after being accessed and external storage. CONSTITUTION:A counter control circuit 6 which is provided with a clock distribution circuit 27 to distribute a clock to blocks corresponding one-to-one to the number of the pages of the main storage and a counter for lapse of time to count up in response to a clock signal from the clock distribution circuit 27, a reset control circuit 38 which resets the counters for lapse of time of all the blocks by a page control request signal, and when some page of the main storage is accessed, resets only the counter for lapse of time of the block corresponding to the page, and a sort circuit which receives the data of a frequency in use counter and the counter for lapse of time, and after re-arranging the data of the frequency in use counter in order from the smaller one, re- arranges the data of the counter for lapse of time in the order from the larger one in respect of a smallest value part are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory page management device.

0002

[Prior Art] In conventional main memory page management, each page has one R bit and one C bit, and when that page is accessed by a read command, only the R bit becomes "1", and by a write command, only the R bit becomes "1". When that page is accessed, both the R bit and C bit become "1". Since that state is maintained, the R bit and C bit are referred to to determine which page has been referenced and which page has been rewritten.

FIG. 4 shows an example of a conventional main memory page management device, and FIG. 5 shows the connection between this main memory page management device and a processor.

0004

[Problems to be Solved by the Invention] In the conventional main memory page management described above, once a page is accessed by a read or write command, the R bit remains at "1". Although it is possible to determine whether or not a file has been referenced, the disadvantage is that the frequency of use and the passage of time cannot be determined, and page-by-page transfer to and from external storage cannot be performed.

[0005]

[Means for Solving the Problems] The main memory page management device of the present invention uses a main memory read signal or a main memory write signal to generate an R bit indicating whether or not a main memory page is referenced, and whether or not this page is rewritten. an R/C bit generation circuit that generates a C bit indicating , a page address generation circuit that takes in an address signal output from another processor and generates a page address, and an R bit output from the R/C bit generation circuit. By taking in the page address signal and RC memory write timing signal from the page address generation circuit, the R/C memory can write the R bit and C bit for each page and temporarily hold the data. , by incorporating a clock distribution circuit that distributes clocks to all blocks in one-to-one correspondence with the same number of pages in the main memory, and by capturing the R bit output from the R/C bit generation circuit for each block. A counter holding unit that has a usage frequency counter that indicates how much the page indicated by the page address generation circuit has been used, and a time elapsed counter that counts up by receiving the clock signal output from the clock distribution circuit. When it receives a page management request signal, it resets the time elapsed counter for all blocks, and when a page in main memory is accessed, it resets only the time elapsed counter for the block corresponding to that page. a reset control circuit that can control the
When receiving a page management request signal from another processor,
Receive the data of the frequency of use counter and the counter for time elapsed from the counter control unit, first rearrange the data of the frequency of use counter in ascending order, and then rearrange the data of the time elapsed counter for the part with the smallest value. The R bit and C bit outputted by a sorting circuit that rearranges them in ascending order and the page address signal and RC memory read timing signal from the R/C memory are processed by receiving an R/C bit information request signal from another processor. It is characterized in that it includes an R/C bit output circuit for outputting to other processors.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the main memory 1 has 64K (to be exact, 2 to the 16th power) pages. FIG. 2 is a detailed diagram of the counter control unit 6 in FIG. 1, and FIG. 3 shows an example of connections between the main memory, the page management device, and the processor.

The command signal output from the processor 32 in FIG. 3 to the command signal line 28 is decoded by the command decoder 29 in FIG. 1, and the result (read signal or write signal) is sent to the main memory read signal line 10 or the main memory write The data is output through a signal line 11 to the main memory 1 having a plurality of pages. At the same time, one page of the main memory 1 is accessed by an address signal output from the processor 32 to the address signal line 12.

The R/C bit generation circuit 2 takes in the signal of the main memory read signal line 10 or the main memory write signal line 11, generates an R bit and a C bit, and generates an R bit signal line 16 and a C bit signal line. 17 respectively R bit signal,
Outputs C bit signal.

Further, the page address generation circuit 3 takes in the address signal output from the processor 32 to the address signal line 12, generates a page address, and communicates it with the R/C memory 4 via the page address signal line 19 for count control. output to section 6.

The R bit and C bit data generated by the R/C bit forming circuit 2 are sent to the page address generating circuit 3.
is written to the address indicated by the page address signal output to the page address signal line 19. The timing of this write is determined by selecting the RC memory write timing signal line 14 by the selector signal 30 (output from the main memory) of the selector 9, and by selecting the timing signal line 18.
According to the timing signal outputted to.

At the same time, the page address signal on the page address signal line 19 causes the counter holding section 37 (FIG. 3) of the counter control section 6 to change the data of the usage frequency counter 41 of the block corresponding to the page whose main memory has been accessed to " 1” is added.

On the other hand, the time counter 42 of the counter holding unit 37 is distributed to all blocks via the clock signal line 40 by the clock distribution circuit 27, and each time a clock signal is input, "1" is added to the counter data. will be added.

Further, the time elapse counter 42 of the block selected by the page address signal line 19 has its counter data reset by a reset signal output from the reset control circuit 38 to the reset signal line 39.

The above operations are performed every time the processor 32 or 33 accesses the main memory 1 and issues a write command or a read command.

Here, when a request signal is output from the processor 32 to the page management request signal line 26, the operation is temporarily stopped after waiting for the above operation to be completed, and is stored in the counter holding section 37. The information data of usage frequency count data and time elapsed counter data for each page are stored in the usage frequency counter data line 20.
Then, the data is transferred to the sorting circuit 7 via the time counter data line 21.

The information data transferred to the sorting circuit 7 is
In order to easily find pages that are used less frequently and for which a long time has elapsed since being accessed, the data in the usage frequency counter 41 is first rearranged in descending order, and then the data in the time elapse counter 42 is sorted for the part with the smallest value. The data is rearranged in ascending order, and the rearranged page management information is output to the page sort result output signal line 25 and transferred to the processor 32.

Note that when a request signal is output from the processor 32 to the page management request signal line 26, the data of the usage frequency counter 41 and the time elapsed counter 42 are transferred to the sorting circuit 7.
After the reset control circuit 38 of the counter control section 6 receives the request signal, the reset signal is distributed to the time elapse counters 42 of all blocks of the counter holding section 37 via the reset signal line 39, and the reset control circuit 38 of the counter control section 6 receives the request signal. All data in the counter 42 is cleared. Thereafter, the processor 32 or 33 accesses the main memory and issues a write command or a read command.

When the processor 32 wants to know only the R/C bit information of a certain page, the processor 32 needs to know the R/C bit information of a certain page.
A request signal is output to the C bit information request signal line 15, and the R/
The signal is taken into the C bit output circuit 8. The page address that other processors want to know is generated by the page address generation circuit 3, and the page address signal and the select signal 30 of the selector 9 are used to generate the RC memory read timing signal line 13.
is selected, and with the timing signal output from the selector 9 to the timing signal line 18, the R bit and C bit signals are output from the R/C memory 4 to the R bit signal line 22 and the C bit signal line 23, respectively. The C bit output circuit 8 outputs the signal to the R/C bit output signal line 24 and transfers it to the processor 32.

[0020]

[Effects of the Invention] As explained above, by employing the above configuration, the present invention enables more accurate page management because it is possible to know the frequency of use and how much time has passed since the last access for each page. This has the effect of finding the least frequently used page and the longest elapsed time since it was accessed, and transferring that page to external storage on a page-by-page basis.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed block diagram of the counter control section in FIG. 1.

FIG. 3 is a connection diagram between a main memory page management device and a processor according to the present invention.

FIG. 4 is a block diagram of the prior art.

FIG. 5 is a connection diagram between a conventional main memory page management device and a processor.

[Explanation of symbols]

1 Main memory 2 R/C bit generation circuit 3 Page address generation circuit 4 R/C memory 5 Register 6 Count control section 7 Sort circuit 8 R/C bit output circuit 9 Selector 10 Main memory read signal line 11 Main memory write signal line 12 Address signal line 13 RC memory write timing signal line 14
RC memory read timing signal line 15
R/C bit information request signal line 16, 22 R
Bit signal lines 17, 23 C bit signal line 18 Timing signal line 19 Page address signal line 20 Usage frequency counter data line 21 Time elapsed counter data line 24 R/C bit output signal line 25 Page sort result output signal line 26
Page management request signal line 27 Clock distribution circuit 28 Command signal line 29 Command decoder 30 Selector signal lines 31, 34 Internal block 32 Processor 33 Processor 35, 36, 40 Clock signal line 37
Counter holding unit 38 Reset control circuit 39 Reset signal line 41 Usage frequency counter 42 Time elapsed counter

Claims (1)

[Claims] 1. An R/C bit generation circuit that generates an R bit indicating whether or not a main memory page is referenced and a C bit indicating whether or not this page is rewritten, according to a main memory read signal or a main memory write signal. , a page address generation circuit that takes in address signals output from other processors and generates a page address, and R bits and C bits output from the R/C bit generation circuit, and a page address signal from the page address generation circuit and RC. By capturing the memory write timing signal, R
An R/C memory that can write bit C bit and temporarily hold the data, and a clock distribution circuit that distributes clocks to all blocks that correspond one-to-one and have the same number of pages as the main memory. And for each block, R
a usage frequency counter that indicates how much the page indicated by the page address generation circuit has been used by capturing the R bit output from the /C bit generation circuit;
A counter control unit including a counter holding unit that has a time elapse counter that counts up when a clock signal output from the clock distribution circuit is input, and a time elapse counter for all blocks when a page management request signal is received. Also, when a page in main memory is accessed, a reset control circuit that can control to reset only the time elapse counter of the block corresponding to that page, and when a page management request signal from another processor is received, the counter Receives the data of the frequency of use counter and the counter for time elapsed from the control unit, first rearranges the data of the frequency of use counter in ascending order, and then increases the data of the time elapsed counter for the part with the smallest value. A sort circuit rearranges the R bits and C bits output by taking in the page address signal and the RC memory read timing signal from the R/C memory, and the R bits and C bits output by taking in the page address signal and the RC memory read timing signal from the R/C memory. 1. A main memory page management device comprising: an R/C bit output circuit for outputting to a processor.