JPH04314366A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve coverage of aluminum sputtering by providing an atmospheric pressure CVD insulating film of a sidewall with a taper formed in both sides of a control gate and an atmospheric pressure CVD insulating film of a layer insulating film formed covering the control gate and the sidewall. CONSTITUTION:A CVD oxide film which is to become a sidewall is formed all over a 5000 to 15000Angstrom wafer. In the process, a CVD oxide film is thicker in a step part of a control gate 8 than in a flat part thereof. Therefore, if anisotropic etching is carried out by a film thickness of the flat part, a sidewall 10 of a desired CVD oxide film is formed at both sides of the control gate. Then, a BPSG film 11 is formed. Thereby, a reflow configuration of a layer insulating film is improved aluminum residue is not produced and etching can be carried out without problems.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure of a semiconductor integrated circuit device that can form a good reflow shape in an interlayer insulating film in an EEPROM LSI or the like.

0002

[Background Art] With the recent demands for higher integration and higher speed in semiconductor integrated circuit devices, the dimensions of the elements included therein are becoming increasingly finer, and interlayer insulating films are also becoming finer and more reliable. It is strongly desired to have an excellent structure.

In a conventional EEPROM, as shown in FIG. 2, after forming a floating gate 5 and a control gate 8, a normal pressure CVD insulating film 11 is formed as an interlayer insulating film. Since the gate is made of two layers of polycrystalline silicon, the gate is higher than the polycrystalline silicon gate of a normal MOSLSI, and the reflow shape of the interlayer insulating film is poor.

0004

[Problem to be solved by the invention] The above-mentioned conventional EEP
In ROM semiconductor integrated circuit devices, as shown in Figure 2, the reflow shape of the interlayer insulating film is poor, so after forming the interlayer insulating film, metal wiring is formed, for example, by sputtering aluminum and dry etching when patterning the aluminum. There was a risk that aluminum would remain in places where aluminum should have been etched, resulting in short-circuit defects.

[0005] Due to such an unstable structure, at a mass production level, variations in the manufacturing process, etc. have led to a decrease in yield.

An object of the present invention is to obtain a stable reflow shape even when the floating gate, control gate, and polycrystalline silicon are in two stages, to prevent manufacturing variations in the interlayer insulating film, and to form a An object of the present invention is to provide a semiconductor integrated circuit device which can improve the coverage of aluminum sputtering and which does not leave unnecessary aluminum during aluminum etching.

[0007]

[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention includes a plurality of element active regions formed on one principal surface of a semiconductor substrate, and a first gate oxide film formed on the element active regions. , a tunnel gate oxide film thinner than the first gate oxide film for passing charges formed on the drain side of the first gate oxide film, and a tunnel gate oxide film formed on the first gate oxide film and the tunnel gate oxide film. The first layer of polycrystalline silicon that will become the formed floating gate and the first
A second gate oxide film and a gate silicon nitride film are formed to insulate the second layer of polycrystalline silicon formed on the second layer of polycrystalline silicon, and a second gate silicon nitride film is formed to cover the aforementioned two layers of insulating film. In a semiconductor integrated circuit device having a second layer of polycrystalline silicon that serves as a control gate, the atmospheric pressure CVD insulating film is a tapered sidewall formed on both sides of the second layer control gate. and normal pressure C as an interlayer insulating film formed covering the second layer control gate and sidewalls.
The structure is characterized by having a VD insulating film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of an EEPROM semiconductor integrated circuit device according to an embodiment of the present invention.

As shown in FIG. 1, following the same process as before,
An N+ layer 2, which will become the source and drain of the EEPROM, is ion-implanted onto a P-type silicon substrate 1, a first gate oxide film 3 and a tunnel gate oxide film 4 are formed, and then a floating gate 5 and a second gate oxide film are formed. 6. Pattern the gate silicon nitride film 7 and control gate 8 to form a polycrystalline silicon oxide film 9. Next, a CVD oxide film, which is to become a sidewall, is grown on the entire surface of the wafer to a thickness of 5,000 angstroms to 15,000 angstroms. At this time, the thickness of the CVD oxide film is thicker in the step part of the control gate than in the flat part, so if anisotropic etching is performed by the thickness of the flat part, the desired CVD oxide film can be formed on both sides of the control gate. A sidewall 10 is formed. Next, a BPSG film is formed.

FIG. 1 is a cross-sectional view after patterning the aluminum wiring 12. Since the reflow shape of the interlayer insulating film is good, no aluminum residue is generated and the wiring is etched without problems.

[0011]

Effects of the Invention As explained above, the present invention has two layers of polycrystalline silicon as the conventional floating gate and control gate, so the gate is higher than the polycrystalline silicon of a normal MOSLSI, and the reflow shape of the interlayer insulating film is improved. However, since CVD oxide film sidewalls are formed on both sides of the control gate, a stable reflow shape can be formed without being affected by manufacturing variations in the interlayer insulating film forming process. This has the effect that it is possible to improve the coverage of aluminum sputtering in the step of forming aluminum wiring, and it is also possible to solve the problem of unnecessary aluminum remaining during aluminum dry etching.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 P-type silicon substrate 2 N+ layer 3 First gate oxide film 4 Tunnel gate oxide film 5 Floating gate 6 Second gate oxide film 7 Gate silicon nitride film 8 Control gate 9 Polycrystalline silicon oxide film 10 CVD oxide film (sidewall) 11
BPSG film 12 Aluminum wiring 13 Aluminum remaining area

Claims (1)

[Claims] 1. A plurality of element active regions formed on one main surface of a semiconductor substrate, and a first element active region formed on the element active region.
a gate oxide film, a tunnel gate oxide film thinner than the first gate oxide film for passing charges formed on the drain side of the first gate oxide film, and the first gate oxide film and the tunnel gate. For insulating the first layer of polycrystalline silicon, which is formed on the oxide film and becomes the floating gate, and the second layer of polycrystalline silicon, which is formed on the first layer of polycrystalline silicon. In a semiconductor integrated circuit device comprising a second gate oxide film, a gate silicon nitride film, and a second layer of polycrystalline silicon serving as a control gate formed covering the two layers of insulating films, the second layer A normal pressure CVD insulating film which is a tapered sidewall formed on both sides of the second control gate, and a normal interlayer insulating film which is formed to cover the second control gate and the sidewall. 1. A semiconductor integrated circuit device comprising a pressure CVD insulating film.