JPH04318971A - Composite semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a surge voltage of an FET to be generated at the time of turning OFF a composite semiconductor device and to realize the-device having a small normal loss in the device in which a static induction(SI) thyristor and a MOS type FET are cascode-connected. CONSTITUTION:In a composite semiconductor device in which an SI thyristor 2 and a MOS type FET 3 are cascode-connected, a resistor R1 having 10-40OMEGA is connected to a gate circuit of the FET 3, a value of a surge voltage at the time of turning OFF is lowered, necessity of using a high withstand voltage MOS type FET is eliminated, a normal loss is reduced, and a turn-off time is set to about 0.5mus to be able to cope with 10-50kHz of a general operating frequency.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a static induction thyristor (S
This invention relates to a composite semiconductor device that combines a MOS type FET (I thyristor) and a MOS type FET.

0002

BACKGROUND OF THE INVENTION In recent years, in the field of power electronics, there has been an increasing demand for semiconductor devices that can handle higher frequencies in order to improve the efficiency and reduce noise of applied equipment. Although SI thyristors are recognized for their excellent high-frequency characteristics, they have the disadvantage of requiring a large current to be drawn from the gate at turn-off, making the gate control circuit more complex and larger in capacity than other devices.

[0003] Therefore, by connecting the cathode of the SI thyristor to the drain of an n-channel MOS FET and the gate of the SI thyristor to the source of the n-channel MOS FET in cascode, it is possible to control the high-speed SI thyristor as a voltage-controlled device. has been reported. (B.J. Baliga, Solid-St.El
ectron. 25, No. 5, pp345-353,
(1982) FIG. 5 shows the above-mentioned cascode-connected composite semiconductor device. In FIG. 5, 1 is a composite semiconductor device;
2 is an SI thyristor, 3 is a MOS type FET, E1 is an ON control power supply, E2 is an OFF control power supply, SW1 is an ON switch, and SW2 is an OFF switch.

In the cascode connection as shown in FIG. 5, unless a completely normally-on type SI thyristor is used as the SI thyristor 2, the on-state characteristics will be significantly poor or the SI thyristor will not turn on at all. A completely normally-on type SI thyristor has a smaller anode voltage that can be blocked with the same gate reverse voltage than a normally-off type SI thyristor. Generally, normally-on type SI thyristors require a gate voltage of 100V or more to block an anode voltage of 1000V. For this reason, the withstand voltage of the MOS type FET 3 also needs to be 100V or higher.

[0005] The on-resistance of a MOS FET is 2.5 times higher than the withstand voltage.
Since it is proportional to the multiplication factor, increasing the withstand voltage of the MOS FET 3 means that the steady loss during cascode connection increases. In order to increase the withstand voltage of the cascode-connected device shown in Figure 5, it is necessary to also increase the withstand voltage of MOS FET 3. Therefore, it is not practical from a loss perspective to configure a device with a voltage of 1000 V or more using the cascode-connected device shown in Figure 5. Not.

On the other hand, the cascode connection shown in FIG. 6 in which a diode D is inserted in the forward direction between the gate of the SI thyristor 2 and the source of the MOS type FET 3 in the cascode connection shown in FIG. 5, and the cascode connection shown in FIG. 7 in which a Zener diode ZD is inserted is also considered. It is being In these cases, the diode D
Since the built-in voltage of ZD or the Zener voltage of Zener diode ZD is applied to SI thyristor 2 as an on-gate voltage, cascode connection can also be used for SI thyristors that are close to normally off, that is, can block large anode voltages with a small gate reverse bias. Ta.

[0007]

[Problem to be Solved by the Invention] FIG. 8 shows the anode current IA and voltage VAK waveforms of the SI thyristor 2 and the MOS type FET 3 at turn-off in the case of the cascode connection shown in FIG.
3 shows an example of the drain-source voltage VDS waveform of FIG. As can be seen from FIG. 8, the drain-source voltage VDS of the MOS type FET 3 jumps once in the early stage of turn-off, and then becomes a substantially constant value.

This jump in the voltage VDS at the initial stage of turn-off is caused by the gate of the SI thyristor 2 and the MOS type FET 3.
d of the current flowing between the inductance between the sources of
It is determined by i/it, and the faster the MOS FET 3 is operated, the larger the value of the surge voltage becomes. Due to this surge voltage, MOS type FET3 is
It is necessary to increase its withstand pressure to prevent it from being destroyed.

As a result, as in the case of the cascode connection shown in FIG. 5, this increases the loss of the device.
, it is also difficult to construct the cascode connection shown in FIG.

The present invention has been made in view of these conventional problems, and its purpose is to
An object of the present invention is to provide a composite semiconductor device that can reduce the surge voltage of a MOS FET that occurs when turning off a device in which a thyristor and a MOS FET are connected in cascode, and can realize a device with low steady-state loss.

[0011]

[Means for Solving the Problems] In order to achieve the above object, a composite semiconductor device according to the present invention connects the cathode of an SI thyristor to the drain of a MOS type FET,
SI thyristor and MOS, in which the gate of the SI thyristor is connected to the source of the MOS type FET and used as the first electrode taken out to the outside, the anode of the SI thyristor is used as the second electrode, and the gate of the MOS type FET is used as the third electrode. In a three-terminal composite semiconductor device consisting of a type FET, the MOS
It is made by inserting a resistor into the gate circuit of a type FET.

Gate of the above SI thyristor and MOS type F
It is preferable to insert a diode in series in the forward direction or a Zener diode between the source of the ET and the source of the ET. Further, it is preferable that the resistance is in the range of 10 to 40Ω.

[0013]

[Operation] In a composite semiconductor device in which an SI thyristor and a MOS FET are connected in cascode, the MOS FET
If a resistor is inserted into the gate circuit of the circuit and its resistance value is varied, the surge voltage generated at the early stage of turn-off becomes smaller as the resistance value increases. Therefore, by inserting a resistor into the gate circuit, the withstand voltage of the MOS FET can be reduced, so that the steady loss during cascode connection can be reduced.

[0014] Also, as this resistance value increases, the turn-off time increases, but if this resistance value is set to about 10 to 40Ω, the turn-off time can be reduced to 10 to 40Ω, which is the normal operating frequency.
The required time at 50 KHz can be about 0.5 μs.

Furthermore, when a forward diode or Zener diode is inserted in series between the gate of the SI thyristor and the source of the MOS FET, the built-in voltage or Zener voltage of the diode becomes the on-gate voltage of the SI thyristor.
Since it is added to the thyristor, a large anode voltage can be blocked by reverse gate bias.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit of a composite semiconductor device according to a first embodiment of the present invention. This embodiment is based on M in the conventional cascode-connected composite semiconductor device 1 shown in FIG.
A resistor R1 is inserted in series with the gate circuit of the OS type FET3.

FIG. 2 shows the magnitude of the surge voltage VDSP generated between the drain and source of the MOS type FET 3, which was measured by varying the value of the resistor R1 in this embodiment, and the magnitude of the surge voltage VDSP and the completely off state. This figure shows the ratio of the drain-source voltage VDS and the turn-off time TOFF when the voltage VDS reaches .

It can be seen from FIG. 2 that as the value of the resistor R1 of this embodiment increases, the value of the surge voltage VDSP decreases. In addition, the turn-off time increases as the value of gate resistance R1 increases, and when it is 50Ω or more, the turn-off time increases by 0.5Ω.
It becomes longer than μs. Generally the operating frequency is 10~50KH
z, it is necessary to set the turn-off time to about 0.5 μs. Therefore, the resistance R inserted into the gate
It is optimal to set the value of 1 to 10 to 40Ω in terms of turn-off time and to avoid increasing steady-state loss when using a high voltage MOS FET.

FIGS. 3 and 4 show circuits of composite semiconductor devices according to second and third embodiments, respectively, of the MOS type FET 3 of the cascode-connected composite semiconductor device 1 shown in FIGS. This is a gate circuit in which a resistor R1 is inserted in series. Similarly to the first embodiment, in the composite semiconductor devices of the second and third embodiments, by appropriately selecting the resistance value of the resistor R1, it is possible to avoid increasing steady-state loss by using a high voltage MOS FET.

[0020]

[Effects of the Invention] Since the present invention is constructed as described above, it produces the following effects.

(1) By inserting a resistor into the gate circuit of the MOS type FET, it is possible to suppress the surge voltage that occurs when the cascode connection is turned off.
It becomes possible to reduce the withstand voltage of the OS type FET by 30% or more compared to the conventional type. Therefore, a composite semiconductor device with low steady-state loss can be obtained.

(2) In claim 4, the resistance value of the resistor is set to 10 to 40Ω, so in addition to the above (1), the off time is set to 0 which is necessary for a general operating frequency of 10 to 50 KHz.
．． The time can be set to about 5 μs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a composite semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a characteristic curve diagram showing the relationship between gate resistance, surge voltage, and turn-off time of the composite semiconductor device in FIG. 1;

FIG. 3 is a circuit diagram showing a composite semiconductor device of a second embodiment.

FIG. 4 is a circuit diagram showing a composite semiconductor device of a third embodiment.

FIG. 5 is a circuit diagram of a composite semiconductor device showing a conventional example of the device in FIG. 3;

FIG. 6 is a circuit diagram of a composite semiconductor device showing a conventional example of the device in FIG. 4;

FIG. 7 is a circuit diagram of a composite semiconductor device showing a conventional example of the device in FIG. 1;

FIG. 8 is a curve diagram showing voltage and current characteristics at turn-off of a conventional composite semiconductor device.

[Explanation of symbols]

1...Composite semiconductor device 2...SI (static induction) thyristor 3...MOS type FET D...Forward diode ZD…Zener diode E1, E2...Control power supply SW1, SW2...switch.

Claims (4)

[Claims] Claim 1: The cathode of the SI thyristor is connected to the drain of the MOS type FET, and the gate of the SI thyristor is connected to the source of the MOS type FET to take it out to the outside.
In a three-terminal composite semiconductor device consisting of an SI thyristor and a MOS FET, in which the anode of the SI thyristor is used as the second electrode, and the gate of the MOS FET is used as the third electrode, the gate circuit of the MOS FET is A composite semiconductor device characterized by the insertion of a resistor. [Claim 2] SI thyristor gate and MOS type F
2. The composite semiconductor device according to claim 1, further comprising a diode inserted in series in the forward direction between the ET source and the ET source. [Claim 3] SI thyristor gate and MOS type F
2. The composite semiconductor device according to claim 1, further comprising a Zener diode connected in series with the source of the ET. 4. The composite semiconductor device according to claim 1, wherein the resistance is in the range of 10 to 40 Ω.