JPH043222A - Data processor - Google Patents

Abstract

PURPOSE:To execute the overflow detection processing at a remarkably high speed by providing a means for controlling an inversion output or a non- inversion output to the arithmetic and logic calculating means of data stored in a first storing means in accordance with the value of the most significant bit of a second storing means. CONSTITUTION:Among the products of (m + n) bits in which a multiplication processing by an arithmetic and logic calculating means (ALU) 35 is obtained by the multiplication of data of (m) bits and data of (n) bits, when the data of the upper digit is stored in a first storing means (B register) 32, and the data of the lower digit is stored in a second storing means (M register) 33, a control means (B register output control circuit) 38 controls the inversion output or a non-inversion output to the arithmetic and logic calculating means of the data stored in a first storing means in accordance with the value of the most significant bit of the second storing means, and the arithmetic and logical calculating means sets a zero detecting bit in accordance with the value of the data stored in the first storing means which is subjected to an inversion output or a non-inversion output. In such a manner, the data processor which can detect an overflow in multiplication at a high speed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device having a multiplication function.

[Conventional technology]

FIG. 4 is a block diagram illustrating the configuration of a portion of a conventional data processing device used for multiplication processing.

In the figure, 1 is a 32-bit wide 81 bus, 2 is a 32-bit wide 82 bus, and 3 is a 32-bit wide D bus.

10 is a constant ROM that stores constants used within the data processing device, and S1 bus 1. It has an output path to the S2 bus 2. 2o is a register file composed of a plurality of 32-bit wide registers, and has an input path from the D bus 3 and an output path to the S1 bus 1 and the S2 bus 2.

31 is the A register, which connects the input path from the S1 bus and the ALU.
A 33-bit wide register with an output path to S
When data is input from bus 1, it is sign-extended or zero-extended to 33 bits, and when output to ALU 35, 33 bits are output as they are. Also, A register 3
It has a function of setting the value of 1 to zero or inverting the value of the A register 31 and outputting it to the ALU 35. 32 is a B register, which is a 33-bit wide register having an input path from the S2 bus 2 and the ALU 35, and an output path to the ALU 35. 33 when inputting data from S2 bus 2.
Bits are sign-extended or zero-extended, and input/output to and from the ALU 35 is performed using 33 bits. Also, you can set the value of the B register 32 to zero or invert the value of the B register 32 to
It has a function of outputting to LLI35. B register 3
2 is combined with the M register 33 and can shift l bits in the left and right direction. 33 is M register, S2 bus 2
It is a 33-bit wide register with an input path from the D bus 3 and an output path to the D bus 3.

When data is input from the S2 bus 2, it is sign-extended or zero-extended to 33 bits, and the lower 32 bits are output to the D bus 3. Note that the A register 31. B
The reason why the register 32 and the M register 33 have a width of 33 bits is because multiplication of signed data and multiplication of unsigned data can be performed in the same way, and 32-bit unsigned data is zero-extended to create 33-bit signed data. This is to convert it into One additional bit 34 is coupled to the LSB side of the M register 33. By combining the M register 33 and the additional bit 34, it is possible to shift one bit to the right. 35 is an arithmetic logic unit (ALU)
Then, an operation is performed between the 33-bit data output from the A register 31 and the B register 32, and the result is output to the D bus 3 or the B register 32. The arithmetic and logic operation circuit (ALU) 35 calculates 33 bits between the 33 bit data, but outputs the lower 32 bits to the D bus 3 and outputs the 33 bit data to the B register 32 as is. In ALU35, addition and subtraction, logical sum, logical product,
Various types of arithmetic processing such as exclusive OR are possible.

36 is a zero flag, which becomes "1" when the calculation result in the ALU 35 is zero, and becomes "0" when the calculation result is other than zero.

37 is a decoding circuit which decodes the LSB value of the M register 33 and 2 bits of the additional bit 34, and sends a signal specifying an operation to the ALU 35. Decode circuit 37
The operation is shown in FIG.

40 is a barrel shifter which can shift multiple bits of 32-bit data at once. Shift width data and shifted data are input from S1 bus 1 and S2 bus 2, respectively, and the shift results are output to D bus 3.

FIG. 5 is a correspondence diagram illustrating the correspondence between the execution operation types of the ALU 35 based on the decoding state of the decoding circuit 37 shown in FIG.

The result of decoding the LSB value of the M register 33 and the 2 bits of the additional bit 34 indicates what kind of operation is specified for the ALU 35.

FIG. 6 is a diagram illustrating a multiplication execution processing sequence in the data processing apparatus shown in FIG. 4. In the following, a case will be described in which 32-bit data is multiplied.

Note that multiplication is first-order B.

It is executed using the oth algorithm. In this method, the lower two bits of the partial product are decoded, and based on the result, the partial product is selected to be added, subtracted, or nothing, and then shifted to the right.

First, data is input into each register. The multiplier is input to the A register 31, and the multiplicand is input to the M register 33. At this time, 32-bit data is expanded to 33-bit data and stored in each register.

Signed data is sign-extended, unsigned data is zero-extended. In this way, by converting 32-bit signed data and 32-bit unsigned data into 33-bit signed data, signed data and unsigned data can be multiplied in the same way. On the other hand, B
Register 32 and additional bit 34 are set to zero.

Next, the decoding circuit 37 decodes the LSB value of the M register 33 and the 2 bits of the additional bit 34, and specifies the arithmetic operation as shown in FIG. 5 to the ALU 35. ALtJ35
The result of the operation executed in is returned to the B register 32. Then, B register 32°M register 33 and additional bit 3
4 and performs an arithmetic shift one bit to the right.

By repeating the operation and right shift of the ALU 35 33 times, a 66-bit product can be obtained in the B register 32 and the M register 33. The B register 32 contains the upper 3
Three bits are stored in the M register 33, and the lower 33 bits are stored. Shift the B register 32 to the left by "1" bit. At this time, the MSB value of the M register 33 is entered into the LSB of the B register 32.

By the method described above, 32-bit data can be multiplied and a 64-bit product can be obtained in the B register 32 and the M register 33.

Here, overflow detection processing will be explained.

When the product is represented by the lower 32 bits, it is necessary to detect an overflow indicating that the product does not fit within the 32 bits. An overflow occurs when all bits of the upper digits do not match the sign bits of the lower digits, so the condition for overflow in the above state after multiplication is that if the data is signed, each bit of the B register 32 When there is a bit that does not match the MSB of the M register 33, the value stored in the B register 32 is non-zero if it is unsigned data. In order to detect overflow, the following processing is required.

First, the value of the M register 33 is output to the D bus 3, and the value is stored in the RO register, which is a register in the register file 20. Next, the value of the RO register is shifted to the right by 32 bits using a barrel shifter, and the result is stored in the R1 register. At this time, an arithmetic shift is performed in the case of signed data, and a logical shift is performed in the case of unsigned data.

In other words, if the value of the RO register is negative for signed data, all bits are 1 ((FFFFFFFFF in hexadecimal)
H)), and the other values are zero. Finally, R1
The value of the register is input to the A register 31 and compared with the value of the B register 32 in the ALU 35. As a result of the comparison, if they do not match, it indicates an overflow, and the zero flag 36 becomes rOJ.

On the other hand, if there is no overflow, the comparison results match and the zero flag 36 becomes "1".

In this way, the presence or absence of overflow can be detected based on the value of the zero flag 36. In other words, if the zero flag 36 is "o", it means overflow, and if the zero flag 36 is "1", it means no overflow.

As mentioned above, there are three processes for detecting overflow in multiplication: ■ reading the product, ■ shifting, and ■ comparing.
Cycle processing is required.

[Problems to be Solved by the Invention] Since the conventional data processing device is configured as described above, in order to detect overflow in multiplication, three steps are required.
There were problems in that it required cycles and the processing time was long.

This invention was made to solve the above problem, and when the sign of the lower digit data of the product is positive, the upper digit data of the product is output as is to the ALU, and when the sign is negative, the sign of the lower digit data of the product is output to the ALU. It is an object of the present invention to provide a data processing device that can detect overflow in multiplication at high speed by controlling the inverted value of high-order digit data to be output to an ALU.

[Means for Solving the Problems] A data processing device according to the present invention processes data stored in a first storage means to an arithmetic and logic operation means according to the value of the most significant bit of the second storage means. A control means for controlling an inverted output or a non-inverted output is provided.

Further, the control means performs arithmetic and logical operations on the data stored in the first storage means according to the value of the most significant bit of the second storage means and information on whether the data is signed data or unsigned data. The device is configured to control an inverted output or a non-inverted output to the device.

[Operation] In the present invention, the multiplication processing by the arithmetic and logic operation means is performed by multiplying m-bit data by n-bit data, and of the (m+n)-bit product, the data in the upper digits is stored in the first storage means. The lower digit data is stored in the second
When the data is stored in the storage means of the second storage means, the control means inverts or non-inverts the data stored in the first storage means to the arithmetic and logic operation means according to the value of the most significant bit of the second storage means. The arithmetic and logic operation means sets the zero detection bit according to the values of the data stored in the first storage means and the data stored in the second storage means, which are inverted or non-inverted.

Furthermore, the multiplication process by the arithmetic and logic operation means is obtained by multiplying m-bit data by n-bit data (m
+n) When the upper digit data of the product of bits is stored in the first storage means and the lower digit data is stored in the second storage means, the control means controls the most significant bit of the second storage means. The arithmetic logic controller controls inverted output or non-inverted output of the data stored in the first storage means to the arithmetic logic operation means according to the value of The arithmetic means sets the zero detection bit according to the value of the data stored in the first storage means, which is an inverted output or a non-inverted output.

[Embodiment] FIG. 1 is a block diagram illustrating the configuration of a part used for multiplication processing in a data processing device showing an embodiment of the present invention, and the same parts as in FIG. 4 are designated by the same reference numerals. It is attached.

In the figure, 3B is a B register output control circuit that controls the output of the B register 32 based on the MSB value of the M register 33 and information on whether the data to be handled is signed or unsigned. A signal line 39 indicates whether the data currently being processed is signed or unsigned.

In the data processing device configured as described above, the multiplication process by the arithmetic and logic operation means (ALU 35 in this embodiment) is performed by multiplying m-bit data by n-bit data, out of the (m+n)-bit product, The upper digit data is stored in the first storage means (B register 32 in this embodiment).
), and when the lower digit data is stored in the second storage means (in this embodiment, the M register 33), the control means (in this embodiment, the B register output control circuit 38)
The arithmetic logic operation means controls inverted output or non-inverted output of the data stored in the first storage means to the arithmetic logic operation means according to the value of the most significant bit of the storage means of the first storage means. A zero detection bit is set according to the value of the data stored in the output first storage means.

In addition, the multiplication process by the ALU 35 is obtained by multiplying m-bit data by n-bit data ( m +
n) When the upper digit data of the product of bits is stored in the B register 32 and the lower digit data is stored in the M register 33, the B register output control circuit 38 outputs the value of the most significant bit of the B register 32. Controls inverted output or non-inverted output of the data stored in the A register 31 to the ALU 35 according to information on whether the data is signed data or unsigned data, so that the ALU 35 outputs inverted output or non-inverted output. A zero detection bit is set from the data stored in the A register 31 and the data stored in the B register 32.

FIG. 2 shows the B register output control circuit 38 shown in FIG.
This is a diagram explaining the operation of the B register 32, and shows how the output of the B register 32 is controlled based on the MSB value of the M register 33 and the contents of the signal line 39, which indicates whether the data to be handled is signed or unsigned. This shows that.

The operation of each part of the data processing apparatus shown in FIG. 1 will be explained below.

First, data is input into each register. The multiplier is input into the A register 31 and the multiplicand is input into the M register 33. At this time, 32-bit data is expanded to 33-bit data and stored in each register.

Signed data is sign-extended, unsigned data is zero-extended. In this way, by converting 32-bit signed data and 32-bit unsigned data into 33-bit signed data, signed data and unsigned data can be multiplied in the same way. On the other hand, B
Register 32 and additional bit 34 are set to zero.

Next, the decoding circuit 37 decodes the LSB value of the M register 33 and the 2 bits of the additional bit 34, and specifies the arithmetic operation as shown in FIG. 5 to the ALU 35. The calculation result executed by the ALU 35 is returned to the B register 32. and,
B register 32°M register 33 and additional bit 34
, and performs an arithmetic shift one bit to the right.

By repeating such ALtJ35 calculation and right shift 33 times, a 66-bit product can be obtained in the B register 32 and M register 33. The B register 32 stores the upper 33 bits, and the M register 33 stores the lower 33 bits. Shift the B register 32 to the left by "1" bit. At this time, the MSB value of the M register 33 is entered into the LSB of the B register 32.

By the method described above, 32-bit data can be multiplied and a 64-bit product can be obtained in the B register 32 and the M register 33.

Hereinafter, overflow detection processing during multiplication processing according to the present invention will be described.

When the product is represented by the lower 32 bits, it is necessary to detect overflow indicating that the product does not fit within the 32 bits. An overflow occurs when all bits of the upper digits do not match the sign bit of the lower digits, so the condition for an overflow in the above state after multiplication is that if it is signed data, the value stored in the B register 32 When there is a bit among the bits that does not match the MSB value of the M register 33, if the data is unsigned data, the value stored in the B register 32 is non-zero. In order to detect overflow, the following processing is required.

First, the value of the A register 31 is set to zero and output to the ALU 35. The value of the B register 32 is output according to instructions from the B register output control circuit 38. That is, when handling signed data, the MSB of M register 33
Only when the value is "1", the value of the B register 32 is inverted and output; otherwise, it is output as is. When handling unsigned data, the MSB of M register 33
Regardless of the value, the value of the B register 32 is output as is. By performing such control, the output from the B register 32 will always be zero if there is no overflow, regardless of the sign of the product or whether it is signed data or unsigned data. The ALU 35 calculates the logical sum of the output from the A register 31 and the output from the B register 32. In other words, the value of the B register 32 is output to the D bus 3 as is. At this time, if there is no overflow, the operation result will be zero, so the zero flag 36 will be "1". If there is an overflow, the calculation result will not be zero, so the zero flag 36 will be rOJ. In this manner, overflow in multiplication can be detected using the zero flag 36.

FIG. 3 is a flowchart illustrating an example of an overflow detection processing procedure in the data processing apparatus according to the present invention. Note that (1) to (10) indicate each step.

When the multiplication process by the ALU 35 is executed, the higher digit of the product is stored in the B register 32 and the lower digit of the product is stored in the M register 33 (1). Next, rOJ is set in the A register 31 (2). It is determined whether the signal line 39 indicates signed data or unsigned data (3), and if it is signed data, the MSB value of the M register 33 is further determined (4). If the MSB value is "l" in this judgment, the value of the B register 32 is inverted and output to the ALU 35. 5) If roJ, the value of the B register 32 is output as is to the ALU 35 (6) On the other hand, step (3)
If it is determined that the data is unsigned data, the value of the B register 32 is output as is to the ALU 35 regardless of the MSB value of the M register 33 (6). By performing such an operation, the output from the B register 32 becomes zero unless an overflow occurs. Next, ALU3
In step 5, the value of the A register 31 (=O) and the output from the B register 32 are logically summed (7), and it is determined whether the operation result is rOJ or not (8). If it is "0", the zero flag 36 is set as " 1” is set, indicating that there is no overflow (
9) On the other hand, if the determination in step (8) is "1", rOJ is set in the zero flag 36, indicating an overflow (lO). In this way, the overflow detection process ends and the process moves on to other processes.

[Effects of the Invention] As explained above, the present invention inverts or inverts the data stored in the first storage means to the arithmetic and logic operation means according to the value of the most significant bit of the second storage means. Since the control means for controlling the inverted output is provided, the output of the first storage means can be outputted to the arithmetic logic operation means so that the high-order digit data of the product becomes zero when there is no overflow for signed data. .

Further, the control means performs arithmetic and logical operations on the data stored in the first storage means according to the value of the most significant bit of the second storage means and information on whether the data is signed data or unsigned data. Since the configuration is configured to control the inverted output or non-inverted output to the means, the high-order digit data of the product is The output of the first storage means can be outputted to the arithmetic and logic operation means so as to be zero.

Therefore, after performing multiplication, it is possible to detect overflow using a zero flag by simply outputting the upper digit data to the arithmetic and logic operation means, and the conventional read processing
It is not necessary to perform bit shift processing, etc., and the overflow detection processing during multiplication processing can be greatly speeded up.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the configuration of a data processing device showing an embodiment of the present invention, and FIG.
A diagram explaining the operation of the register output control circuit, FIG. 3 is a flowchart explaining an example of an overflow detection processing procedure in the data processing device according to the present invention, and FIG. 4 is a part used for multiplication processing in the conventional data processing device. FIG. 5 is a block diagram explaining the configuration of the decoding circuit shown in FIG. 4, and FIG. FIG. 2 is a diagram illustrating a multiplication execution processing sequence in the data processing device. In the figure, 1 is the S1 bus, 2 is the S2 bus, 3 is the D bus, 10 is the constant ROM, 20 is the register file, 31 is the A register, 32 is the B register, 33 is the M register, 3
4 is an additional bit, 35 is an ALU, 36 is a zero flag, 3
7 is a decoding circuit, 38 is a B register output control circuit, 3
9 is a signal line, and 40 is a barrel shifter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) An arithmetic logic operation means that performs arithmetic operations on m-bit data and n-bit data, and (m+n) obtained by multiplying m-bit data and n-bit data.
(m+n) obtained by multiplying m-bit data and n-bit data by a first storage means having an output path to the arithmetic and logic operation means for storing the data of the upper digits of the product of bits; A data processing device comprising a second storage means for storing data of a lower digit of a product of bits, and a zero detection bit whose logical state is set according to a calculation result in the arithmetic and logic operation means, and control means for controlling inverted output or non-inverted output of the data stored in the first storage means to the arithmetic and logic operation means according to the value of the most significant bit of the storage means. data processing equipment. (2) The control means performs the arithmetic operation on the data stored in the first storage means according to the value of the most significant bit of the second storage means and information on whether the data is signed data or unsigned data. 2. The data processing device according to claim 1, wherein the data processing device controls an inverted output or a non-inverted output to the logical operation means.