JPH0635669A - Central processing unit - Google Patents

Abstract

(57) [Summary] [Purpose] To improve the calculation speed by simultaneously adding multiple sets of data. [Structure] Each 1-bit full adder 1 forming a parallel adder
The carry signal of 3a to 13d is not transmitted to the 1-bit full adders 13a to 13d of the next digit, and the carry signal is reflected in the carry bit of the flag register 16 to give the CPU 11 to the parallel adder 12. Each of the one set of data (two data) is regarded as a set of a plurality of data having a size smaller than the data size of the one set of data, and the respective data are added simultaneously without interfering with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit capable of high speed addition and multiplication in a microcomputer.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a central processing unit having a conventional arithmetic logic operation unit, in which 1 is an arithmetic logic operation unit (hereinafter referred to as ALU) having a parallel adder. Is a data bus, 3 and 4 are A
Registers for temporarily holding data to be input to LU1, A register and B register, 5 are M registers used for multiplication, and 6 are S registers for temporarily holding operation results by ALU1.

Reference numeral 7 is an ALU 1 and registers 3 to 6,
A central processing unit (hereinafter referred to as CPU), which is composed of an instruction decoding unit (not shown) that decodes an instruction, and a control unit that controls the ALU 1 and each of the registers 3 to 6 according to the result decoded by the instruction decoding unit, 8 Is memory. In addition,
The ALU1 performs addition, multiplication and other processing of 32-bit data. Each of the registers 3 to 6 is a 32-bit register.

Next, the operation will be described. First, the addition method will be described with reference to the memory map of FIG. In the memory map shown in FIG. 7, 16-bit data (data) _C stored in the data storage area C and 16-bit data (data) C ′ stored in the data storage area _C ′
Adding, 'operations and stored in a 16-bit data stored in the data storage area D (data) _D and a data storage area D' data storage area C '16-bit data stored in the (data) _D A case where the operation of adding "and storing in the data storage area D" is performed will be described with reference to FIG.

In order to perform the above two additions, the CPU 7
Is two instructions (ADD C C'C '') and (ADD D
D'D '') is executed. Introduction Command (ADD C
C'C '') is executed (FIG. 8A). Command (ADD
C C'C '') is executed, first, A register 3
Data (data) _C is stored in the
The data (data) _C 'is stored in.

Here, the data (data) _C and (data) held in the A register 3 and the B register 4, respectively.
_The ALU 1 adds _C ′ and outputs the result to the S register 6. The addition result held in the S register 6 is stored in the data storage area C ″ of the memory 8 and the instruction (ADD C C ′
C ″) ends.

Next, the instruction (ADD D D'D '') is executed (FIG. 8B). Command (ADD D D'D '')
Is executed, first, the data (data) _D is held in the A register 3, and subsequently, the data (data) _D ′ is held in the B register 4.

Here, the ALU 1 adds the data (data) _D and (data) _D' held in the A register 3 and the B register 4, respectively, and outputs the result to the S register 6. S
The data held in the register 6 is stored in the data storage area C ″ of the memory 8 and the execution of the instruction (ADD D D′ D ″) ends.

The order in which the instructions (ADD C C'C '') and (ADD D D'D '') are executed may be reversed. The above operation is performed by the CPU by means not shown.
The instruction given to the CPU 7 is decoded by an instruction decoding unit (not shown) of the CPU 7, and the control unit (not shown) controls the ALU 1 and the registers 3 to 6 using the decoded result.

Next, an ALU incorporating a conventional parallel adder
A multiplication method by the CPU 7 having 1 will be described with reference to FIG. FIG. 9 shows only changes in the data held in the registers 3 to 6. First, a multiplication instruction (MUL EF) is given to the CPU 1 by means not shown. Here, although not shown, E and F indicate data storage areas. This data storage area may be a memory or a register.

In the data storage areas E and F, two 16-bit data (data) _E = (E ₁₅ , E ₁₄ , ...
., E ₁ , E ₀ ) (EX = 0 or 1) and (data) _F
= (F ₁₅ , F ₁₄ , ..., F ₁ , F ₀ ) (FX = 0 or 1) are stored respectively, and in this instruction, (data) _E is a multiplicand and (data) _F is a multiplier. Suppose

Next, the (data) _E is held in the A register 3, the (data) _F is held in the M register 5, and the value "0 '" is held in the B register (FIG. 9). The ALU 1 fetches the data “0 ′” held in the B register 4, and adds the data “data _E ” stored in the A register 3 or the data “0 ′” instead of the data (data) _E. , B register 4 is again held (see FIG. 9).
). Which data is added depends on the least significant bit of the data held in the M register 5.

That is, as indicated by the arrow α in FIG.
A control unit (not shown) monitors the least significant bit of the data held in the M register 5. If this least significant bit is "1", (data) _E is added and if it is "0". For example, data “0 ′” is added.

Subsequently, the data held in the B register 4 is shifted right by 1 bit. At this time, one bit out of the B register 4 comes out, but this one bit is put in the most significant bit of the M register 5. For this reason,
The (data) _F held in the M register is also shifted right by 1 bit, and the least significant bit `F0 'is discarded outside the M register 5 (FIG. 9).

Next, the ALU 1 takes in the data held in the B register 4 into the ALU 1 and stores the data (data) _E stored in the A register 3 or the data ‘data‘ _E ’instead of the data _E. The operation of adding 0'and holding it in the B register 4 again is performed (FIG. 9). The determination of which data to add is made in the same manner as above.

Then, the data held in the B register 4 is shifted right by 1 bit. At this time, the B register 4 also comes out to the outside of 1 bit, but this 1 bit is put into the most significant bit of the M register 5. Therefore, the data (data) _F held in the M register 5 is also 1
It shifts to the right by a bit and the least significant bit is discarded out of the M register 5 (FIG. 9).

In this way, FIG. 9 and 2 shown in FIG.
After one operation is repeated 14 times, the data spanning the B register 4 and the M register 5 shown by the diagonal lines in FIG. 9 is the multiplication result.

[0018]

Since the conventional central processing unit is configured as described above, addition of one set of data (two data) having a data size smaller than the data size that can be added by the adder is added. However, there is a problem that the addition of two or more sets of data cannot be performed at the same time, resulting in a slower operation speed of addition and multiplication.

The present invention has been made to solve the above problems, and a central processing unit capable of speeding up the processing speed of addition and multiplication by simultaneously processing two or more data. Aim to get.

[0020]

A central processing unit according to the present invention includes an arithmetic logic operation unit having a parallel adder formed of a plurality of 1-bit full adders, and an input / output of the arithmetic logic operation unit. A plurality of registers for temporarily holding data and controlling the operations of the arithmetic logic operation unit and the respective registers according to a given instruction. In the adding operation by the parallel adder, the 1-bit full addition is performed. The carry signal of the multiplier is reflected on the carry bit of the flag register without being transmitted to the next 1-bit full adder.

[0021]

The central processing unit according to the present invention supplies one set of data (two data) to the adder,
It is regarded as a set of a plurality of data having a size smaller than the data size of the one set of data, and the respective data are added simultaneously without interfering with each other.

[0022]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a parallel adder according to the present invention. Figure 2
12 is a 32-bit parallel adder composed of 32 1-bit full adders. This is one of 32 1-bit full adders 13a to 13b, 13c to 13d and 1 bit full adders 13a to 13d. Carry signal line 14a-
14d respectively.

Further, 3 and 4 are registers for temporarily holding the data inputted to the parallel adder 12, A and B registers, and 6 is an S register for temporarily holding the addition result. Each register 3, 4 and 6 is the same as that shown in FIG.

Next, the operation will be described. Here, the operation when the parallel adder 12 adds the 32-bit data G and H will be described with reference to FIG. In FIG. 2, reference numeral 15 denotes a switch for switching the connection of the carry signal 14b of the full adder FA15. The upper 16 bits of the data G are G1, the lower 16 bits are 62, and the upper 16 bits of the data H are H1 and the lower. 16 bits are set to H2.

Now, assume that the data G and H are held in the A register 3 and the B register 4 as shown in FIG. The control unit (not shown) includes a switch 15 as a switch unit.
1 is switched as shown in FIG. 1, and if a carry occurs in the 1-bit full adder 13b, the carry information is transmitted to the flag register 16 without being transmitted to the 1-bit full adder 13c. The carry flag (hereinafter,
CF0 is set (referred to as carry flag).

Next, the upper 16 bits G of the data G and H
1, H1 to the 1-bit full adders 13c to 13d
The 6 bits G2 and H2 are input to the full adders FA0 to FA15 to perform addition, and the result is output to the S register 6. Since the carry of the 1-bit full adder 13b is not transmitted to the full adder 13c, the upper 16 bits of the data held in the S register 6 becomes a value obtained by adding G1 and H1, and the data held in the S register 6 The lower 16 bits have a value obtained by adding G2 and H2.

When a carry occurs in the 1-bit full adder 13b, the switch 15 transmits the carry information to the flag register 16 to carry the flag C.
Set F0. When a carry occurs in the 1-bit full adder 13d, the carry signal line 14d transmits the carry information to the flag register 16 to set the carry flag CF1.

That is, in the parallel adder 12 shown in FIG. 2, 32 held in the A register 3 and the B register 4 is held.
The lower 16 bits and the upper 16 bits of the bit data can be regarded as separate data, and the upper 16 bits and the lower 16 bits can be added independently and simultaneously, and the addition results are It is output to the upper 16 bits and the lower 16 bits of the S register.

FIG. 3 shows the connection between the CPU 11 having the ALU 21 containing the parallel adder 12 shown in FIG. 2 and the memory 8. In the figure, reference numerals 2 to 6 and 8 are the same as those in FIG. Further, 21 is the above-mentioned ALU incorporating the parallel adder 12 in FIG. 2, and 16 is a flag register similar to that shown in FIG. CPU1 here
1 is an ALU 21, a data bus 2, respective registers 3, 4,
It is composed of 5, 6, and 16.

In FIG. 3, 16-bit data (data) _C stored in the data storage area C of the memory map shown in FIG. 7 and 1 stored in the data storage area C '.
The operation of adding 6-bit data (data) _C'and storing it in the data storage area C '' and the 16-bit data (data) _D stored in the data storage area D and the data storage area D ' The operation of adding the 16-bit data (data) _D ′ and storing it in the data storage area D ″ is performed.

In order to perform the above operation, the CP shown in FIG.
An addition instruction (ADDW II'I '') is prepared in U11. Here, I is a 32-bit data storage area including the data storage area C and the data storage area D, and I ′.
Is a 32-bit data storage area including the data storage area C ′ and the data storage area D ′, and I ″ is a 32-bit data storage area including the data storage area C ″ and the data storage area D ″. is there.

Now, the addition instruction (ADDW I I '
I ″) is executed, first, the data (data) _C and (data) _D stored in the data storage area I are held in the A register 3, and subsequently stored in the data storage area I ′. The stored data (data) _C'and (data) _D' is held in the B register 4.

The ALU 21 has an A register 3 and a B register 4
The upper 16 bits ((data) _C and (data) _C ') and the lower 16 bits ((data) _D and (data) _D ') of the 32-bit data held in are added independently and simultaneously. And outputs it to the S register 6.

At this time, if a carry occurs in the addition of the upper 16 bits, the carry flag C of the flag register 16 is used.
F1 is set, and if a carry occurs in the addition of the lower 16 bits, the carry flag CF0 of the flag register 16 is set. The addition result held in the S register 6 is stored in the data storage area I ″ of the memory 8 and the instruction (ADDW
I I'I '') ends.

Example 2. FIG. 4 is a parallel adder 1 shown in FIG.
In the CPU 28 having the ALU 21 incorporating 2
The configuration when multiplication is performed is shown. In the figure, 2 is a data bus, 6 is an S register, and 21 is the above ALU incorporating a parallel adder 12.

Reference numerals 22, 23, 24 and 25 are ALU2.
16-bit registers for temporarily holding the data to be input to 1, A1 register, A2 register, B1 register, B2 register, 26 and 27 are registers used at the time of multiplication, respectively, M1 register, M2 register, 2
8 is an ALU 21, a data bus 2, and registers 22 to 2
7. The CPU is composed of an instruction decoding unit (not shown) and a control unit (not shown).

Further, the A1 register 22 and the A2 register 23 are obtained by dividing the A register 3 in FIG. 6 into halves, and the B1 register 24 and the B2 register 25 are obtained by dividing the B register 4 in FIG. 6 into halves.
The M1 register 26 and the M2 register 27 are obtained by dividing the M register 5 in FIG. 6 into halves.

Each of the registers 22 to 27 is not normally divided, and has the same structure as that of FIG. 6, and is divided when the multiplication instruction shown below is executed to have the structure shown in FIG. The ALU 21 has the built-in parallel adder 12 shown in FIG. 2, and although not shown, the A1 register 22 and the B1 register 24 have the upper 16 bits of the parallel adder 12 as A2.
The register 23 and the B2 register 25 are connected to the lower 16 bits of the parallel adder 12.

Therefore, when the ALU 21 performs multiplication,
16 held in A1 register 22 and B1 register 24
Bit data addition and 16-bit data held in the A2 register 23 and the B2 register 25 can be added simultaneously and independently.

Next, the multiplication method by the CPU 28 shown in FIG. 4 will be described with reference to FIG. In FIG. 5, each register 22
Only changes in data held in ~ 27 are shown. First CP
The U28 executes a multiplication instruction (MULTIW E by means not shown).
F) is given. Here, E and F indicate a data storage area (not shown) (this data storage area may be a memory or a register).

In the data storage areas E and F, two 16-bit data (data) _E = (E ₁₅ , E ₁₄ , ...
., E ₁ , E ₀ ) (EX = 0 or 1) and (data) _F
= (F ₁₅ , F ₁₄ , ..., F ₁ , F ₀ ) (FX = 0 or 1) are stored. In this command,
Let (data) _E be the multiplicand and (data) _F be the multiplier.

Next, (data) _{E is transferred} to the A1 register 22 and A
2 It is held in the register 23. (Data) _F upper bits of the (data) _F1 to M1 register 26, respectively holding the lower 8 bits (data) _F2 to M2 register 27. B1
The register 24 and the B2 register 25 are cleared (see FIG. 5).
).

As shown in FIG. 5, the ALU 21 takes in the data "0 '" held in the B1 register 24,
Add (data) _E stored in the A1 register 22 or add data ‘0’ instead of (data) _E ,
The operation of holding again in the B1 register 24 is performed. Which data is added depends on the least significant bit of the data held in the M1 register 26.

That is, as indicated by the arrow α1 in FIG.
A control unit (not shown) monitors the least significant bit of the data held in the M1 register 26, and if this least significant bit is "1 ', (data) _E is added and" 0 "
If so, the addition of the data “0 ′” is performed.

At the same time, the ALU 21 takes in the data "0 '" held in the B2 register 25 and stores it in A2.
An operation of adding the data (data) _E stored in the register 23 or data “0 ′” instead of the data (data) _E and holding it in the B2 register 25 again is performed.
Here again, which data to add is determined by the least significant bit of the data held in the M2 register 27.

That is, as shown by the arrow α2 in FIG.
A control unit (not shown) monitors the least significant bit of the data held in the M2 register 27, and if this least significant bit is "1 ', the data (data) _E is added,
If it is "0", the data "0" is added.

Then, the data held in the B1 register 24 is shifted right by 1 bit. At this time, one bit out of the B1 register 24, but this 1
The bits are placed in the most significant bits of M1 register 26. Therefore, the (data) _F1 held in the M1 register 26 is also shifted right by 1 bit, and the least significant bit'F8 '
Are discarded out of the M1 register 26. The same operation is performed on the B2 register 25 and the M2 register 27 (FIG. 5).

Next, as shown in FIG. 5, the ALU 21 transfers the data held in the B1 register 24 to the ALU 21.
An operation is performed in which the data (data) _E which is fetched inside and held in the A1 register 22 or data "0 '" is added instead of the data (data) _E and the data is held in the B1 register 24 again. The determination of which data to add is made in the same manner as above.

At the same time, the ALU 21 takes in the data held in the B2 register 25 into the ALU 21, and stores the data (data) _E held in the A2 register 23 or the data (data) _E instead of the data (data) _E. An operation of adding “0 ′” and holding it again in the B2 register 25 is performed. The determination of which data to add is made in the same manner as above.

Then, as shown in FIG. 5, the data held in the B1 register 24 is shifted to the right by one bit.
At this time, the B1 register 24 also comes out of the 1 bit, but the 1 bit is put in the most significant bit of the M1 register 26. Therefore, the (data) _F1 held in the M1 register 26 is also shifted right by 1 bit,
The least significant bit F9 is discarded out of the M1 register 26. The same operation is performed on the B2 register 25 and the M2 register 27.

After repeating the above two operations 7 times, the data held in the B2 register 25 and the M2 register 27 is shifted to the right by 4 bits. As a result, the position is shifted to the position indicated by the shaded β. Finally, the result obtained by adding the data indicated by the diagonal lines γ and δ is the multiplication result.

[0052]

As described above, according to the present invention, an arithmetic logic operation unit having a parallel adder formed of a plurality of 1-bit full adders and input / output data of the arithmetic logic operation unit are temporarily stored. A plurality of registers for holding and controlling the operation of the arithmetic logic operation unit and each of the registers according to a given instruction,
In the addition operation by the parallel adder, the carry signal of each 1-bit full adder is configured to be reflected in the carry bit of the flag register without being transmitted to the next 1-bit full adder. Since it is possible to perform addition of two or more sets of data, it is possible to obtain one that can perform addition and multiplication at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a parallel adder in a central processing unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of a parallel adder shown in FIG.

FIG. 3 is a block diagram showing a data addition method by the central processing unit in the embodiment of the present invention.

FIG. 4 is a block diagram showing a data multiplication method by the central processing unit in the embodiment of the present invention.

5 is an explanatory diagram showing a calculation method when multiplication is performed in FIG.

FIG. 6 is a block diagram showing a conventional central processing unit.

FIG. 7 is a memory map diagram showing data contents of the memory in FIG.

8 is a block diagram showing a method of adding data by the central processing unit in FIG.

9 is an explanatory diagram showing a data multiplication method by the central processing unit in FIG.

[Description of Reference Signs] 3 A register (register) 4 B register (register) 5 M register (register) 6 S register (register) 12 Parallel adder 13a to 13d 1-bit full adder 15 Switch (switch means) 16 Flag register 21 ALU (arithmetic and logic unit) 22 A1 register (register) 23 A2 register (register) 24 B1 register (register) 25 B2 register (register) 26 M1 register (register) 27 M2 register (register)

[Procedure amendment]

[Submission date] December 8, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0052

[Correction method] Change

[Correction content]

[0052]

As described above, according to the present invention, an arithmetic logic operation unit having a parallel adder formed of a plurality of 1-bit full adders and input / output data of the arithmetic logic operation unit are temporarily stored. A plurality of registers for holding and controlling the operation of the arithmetic logic operation unit and each of the registers according to a given instruction,
In the addition operation by the parallel adder, the 1 bit
Since the carry signal of the full adder is reflected to the carry bit of the flag register without being transmitted to the 1-bit full adder of the next stage, one addition adds two or more data groups. Therefore, it is possible to obtain the one capable of performing addition and multiplication at high speed.

Claims (1)

[Claims] 1. An arithmetic logic operation unit containing a parallel adder composed of a plurality of 1-bit full adders, and a plurality of registers for temporarily holding input / output data of the arithmetic logic operation unit are provided. In a central processing unit for controlling the operations of the arithmetic logic operation unit and the respective registers according to the instruction, the carry signal of each 1-bit full adder is added to the next 1-bit full in the addition operation by the parallel adder. A central processing unit, comprising switch means for reflecting the carry bit of a flag register without transmitting it to an adder.