JPH04322331A - Multitask controller - Google Patents

Abstract

PURPOSE:To reduce the memory capacity used for management of each task and to perform the operation processing of management information at a high speed in a real time OS consisting of an 8-bit microprocessor. CONSTITUTION:A task control block arranging means 2 is provided which arranges task control blocks 4, 5, and 6 with 256 bytes as one page so that they are stored in management addresses 0 to 255 on a memory 3 designated by a page input means 11, and lower 8 bits of arrangement address information of a task connection pointer or a connection queue 7 indicating the task connection are reserved to indicate the connection destination, and upper 8 bits are regarded as 0 to perform the connection management of tasks, thereby obtaining a multitask controller which has the small memory capacity and performs the processing at a high speed.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a multitasking operating system for causing one microprocessor to process programs having a plurality of unique purposes (hereinafter referred to as tasks), in which each task queues various queues. The present invention relates to a multitask control device when configuring it.

0002

2. Description of the Related Art In recent years, multitasking control devices have been developed as 8-bit real-time operating systems (hereinafter referred to as real-time OS) to enable a single microprocessor to execute multiple tasks while switching between them and to utilize resources effectively. It has also been applied to inexpensive microprocessors such as microprocessors.

However, the more it is applied to inexpensive but low-function microprocessors, the more real-time O.
Memory redundancy and task execution overhead when using S are problems.

[0004] A conventional multitasking control device will be explained below. Generally, in a real-time OS, the task control information necessary to switch and execute each task is stored in blocks for each task, and these are called task control blocks (hereinafter referred to as TCBs).

FIG. 6 is a functional block diagram of a conventional multitasking control device that is an 8-bit microprocessor with a 64K byte address space and has three tasks.

In FIG. 6, TCB initialization information 601 is a read-only file in which initial information of each TCB is recorded. The TCB placement means 602 reads initial information for generating a TCB from the TCB initialization information 601, generates a TCB, and then places it at an arbitrary address on the memory 603. It is placed. The memory 603 stores the arranged TC
The TCBs 604 to 606 of the first to third tasks are used to store TCBs and connection queues.
02, the contents of which are shown in FIG. 7(a), which will be described later. The connection queue 607 indicates the address of the TCB at the head of the queue. The task connection management means 608 operates each TCB and manages the task queue.

FIG. 7(a) shows the memory 603 in FIG.
It is one of the TCBs 604 to 606 of each task arranged above, and is a TCB configuration diagram showing an example of a conventional configuration.

In FIG. 7(a), 701 is a 16-bit task connection pointer that stores the TCB address of the next task in order to indicate the connection of tasks and configure the queue when configuring various queues. . 702-7
05 is other task management information, which is structured as follows, for example.

[0009] 702 is 8-bit information indicating the task status, and the status of the task, such as whether the task is in an execution state or a dormant state, is saved, and 703 is 8-bit information indicating the task priority. A 16-bit timeout counter 704 performs task time management when the task is in a time waiting state. 705 is a 16-bit task stack pointer, and the stack pointer is saved when the corresponding task is no longer in the execution state.

FIG. 7(b) is a TCB connection diagram showing an example of TCB connection, and shows, for example, a queue of tasks when waiting for execution.

In FIG. 7(b), a connection queue 711 is a task head instruction means, and the T of the head task in the queue is
It is a 16-bit connection queue that indicates the CB address divided into upper and lower parts of 8 bits each. Task connection pointers 712, 713, and 714 are task connection instructing means, and point to the TCB address of the task waiting next to the task.

The connection queue 607, TCB 604 of the first task, TCB 605 of the second task, and TCB 606 of the third task in FIG. 6 are the connection queue 711, TCB 713 of the first task, and TCB 713 of the second task in FIG. T
CB712 corresponds to TCB714 of the third task.

The conventional multitask control device configured as described above will be explained below with reference to FIGS. 6, 7(b), 8, and 9.

First, the TCB placement means 602 of FIG.
Receives TCB initial information from CB initialization information 601, generates TCB for each task, and sequentially writes TCB from any location in memory 603 (here, from address 13F9 (hexadecimal display)).
Place CB. TCB 6 located on memory 603
04 to 606 are thereafter managed by the task connection management means 608. Details of the processing by the TCB placement means 602 and the task connection management means 608 are shown in FIGS. 8 and 9.

FIG. 7B shows a matrix of task control blocks when the order of tasks waiting to be executed is second task - first task - third task.

The contents of the connection queue 711 indicate the start address of the TCB 712 of the second task which is the head of the queue,
Its content is 1401 (in hexadecimal), and the content of the task connection pointer of TCB 712 of the second task is 1401 (in hexadecimal).
13 to indicate the start address of TCB 713 of the task.
F9 (hexadecimal representation), TCB71 of the first task
The contents of the task connection pointer in No. 3 are the TCB of the third task.
714 is 1409 (hexadecimal notation).

The content of the task connection pointer of TCB 714 of the third task is a special code (for example, FFFF (hexadecimal notation)) indicating that there is no TCB connected after this.
becomes.

[0018] In this way, a queue is constructed by sequentially pointing to the leading address of each TCB.

FIG. 8 shows the TCB arrangement means 602 in FIG.
FIG. 2 is a flow diagram showing the processing of FIG. In FIG. 8, step 801 is the initial value 13F9(1
(in hexadecimal notation) and the task count value N. Step 802 reads the initialization information of the Nth TCB, step 803 generates a TCB, and step 804 places the generated TCB in order from the placement address. Step 805 contrasts the next TCB by moving the placement address by the size of the TCB for the next TCB and increasing N by one. step 80
Step 6 looks at the next TCB initialization information and determines whether there are any more tasks. If there are, the process proceeds to step 802; if not, the process ends.

FIG. 9 shows the task connection management means 605 of FIG.
FIG. 9, step 901 reads the lower 8 bits of the connection queue 607 of FIG. 6, and step 902 reads the connection queue 607 of FIG.
After reading the upper 8 bits of 7, step 903 transfers the data read in steps 901 and 902 to TC.
B address information. In step 904, it is determined whether there is a next TCB. If there is, the process returns to the next step 905. If there is no TCB, the process proceeds to step 907 and the TC
Connect B. Step 905 reads the lower 8 bits of the task connection pointer of the TCB, and then step 906 reads the upper 8 bits of the task connection pointer of the TCB.
The bit is read and the process returns to step 903.

[0021]

[Problems to be Solved by the Invention] However, in the above configuration, 16-bit memory is used for the connection queue and the task connection pointer of each TCB, which uses a large amount of memory and at the same time When referring to the queue 711 or the task connection pointer 712, an 8-bit microprocessor requires accessing the memory twice to obtain 16-bit information, which poses a problem in that it takes time.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a multitask control device that can reduce the size of connection queues and task connection pointers, and can perform processing at high speed.

[0023]

[Means for Solving the Problems] The present invention provides N task control blocks that store task management information necessary for switching and executing multiple tasks, and writing arbitrary information by specifying a management address. a readable memory means; a page input means for specifying a memory page at an address in which the N task control blocks are arranged, with 256 bytes as one page; and a page input means for specifying the page input of the N task control blocks. task control block arrangement means for arranging a task control block in a predetermined address space so as to be placed in a management address from address 0 to address 255 in one page of the memory inputted by the means; In order to configure a queue of tasks, N task connection instruction means are used to indicate the connection of tasks by saving the lower 8 bits of the arrangement address information of the task control block of the next task to be connected, and Task header indicating means for storing the lower 8 bits of placement address information of the task control block of the task to indicate the header task, and placement start address detection means for detecting the header address information of the N task control blocks. and a placement end address detection means for detecting the last address information of the N task control blocks, and two addresses detected by the placement start address detection means and the placement end address detection means are on the same page. The result of the address determination means and the address comparison means is 256.
and warning issuing means for issuing a warning if the above is the case.

[0024]

[Operation] With the above-described configuration, the present invention allows the task control block allocation means to divide the TCB of each task into 256 bytes.
Management address 0 to 2 of page memory specified as page
55 address, and the task head instruction means and task connection instruction means are placed in the lower 8 addresses of the address information.
By specifying bits, TCB operations such as task connection processing can be performed using 8-bit operations, resulting in faster processing. Also, since the connection queue and the task connection pointer that makes up the TCB can be configured with 8 bits, memory The usage amount can be reduced.

[0025]

[Embodiment] FIG. 1 shows a first embodiment (claim 1) of the present invention, which is an 8-bit microprocessor with an address space of 64 Kbytes, the number of tasks N=3, and a page input means. FIG. 2 is a functional block diagram showing the configuration of the multitask control device when 7 is input.

In FIG. 1, reference numeral 1 indicates TCB initialization information in which initial information necessary for generating a TCB is stored; reference numeral 11 indicates page input means for inputting a memory page in which a TCB is to be placed, with 256 bytes as one page; Reference numeral 2 denotes a TCB placement means that creates a TCB based on the TCB initialization information 1 and places it sequentially from address 0 on the page designated by the page input means 11 on the memory 3. 3 is a memory for arranging TCBs and connection queues; 4, 5, and 6 are each provided by the TCB arranging means 2;
These are the TCBs of the first to third tasks arranged in order from address 0 in the memory 3. 7 is the TCB of the first task in the queue
This is a connection queue that indicates the lower 8 bits of an address, and does not need to exist at addresses 0 to 255. 8 denotes TCBs 4 to 6 of each task arranged on the memory 3 of the memory page input by the page input means 11, and a connection queue 7.
This is a task connection management means that configures and manages a task connection matrix by manipulating the task connection matrix.

FIG. 2A is a TCB configuration diagram showing an example of the configuration of a 7-byte TCB, which is one of the TCBs 4 to 6 of each task arranged on the memory 3 in FIG.

In FIG. 2(a), 201 indicates the connection of tasks when configuring various queues and configures the queue, so the lower 8 of the TCB address of the next task is
It is an 8-bit task connection pointer that only stores bits.

202 to 205 are other task management information, and here, 702 to 705 in FIG. 7(a) of the conventional example
is configured exactly the same.

FIG. 2(b) is a TCB connection diagram showing an example of TCB connection, and shows, for example, a queue of tasks when waiting for execution.

In FIG. 2(b), the connection queue 211
is a task head instruction means, which is an 8-bit connection queue that points only to the lower TCB address of the head task in the queue.

[0032] Task connection pointers 212, 213, 21
4 is a task connection instruction means, which indicates the lower 8 bits of the TCB address of the task waiting next to the task.

Connection queue 7, first task TCB 4, second task TCB 5, and third task TCB in FIG.
6 are the connection queue 211 of FIG. 2(b), the TCB 213 of the first task, the TCB 212 of the second task, and the third task, respectively.
It corresponds to the TCB 214 of the task.

The operation of the multitask control device of this embodiment constructed as described above will be explained below with reference to FIGS. 1, 2(b), 3, and 4.

In FIG. 1, when a TCB arrangement memory page (page 7 in this case) is input from the page input means 11, the TCB arrangement means 2 receives TCB initial information from the TCB initialization information 1, creates a TCB, and stores it in the memory. 0700, which is the top of the 7th page of
(Displayed in hexadecimal) Arrange in order starting from address. The TCBs 4, 5, and 6 arranged on the memory 3 receive arrangement page information from the page input means 11 to the task connection management means 8, and manage them based on this page information.

FIG. 2B shows the queue of the task control block when the order of tasks waiting to be executed is second task - first task - third task.

The contents of the connection queue 211 are the lower 8 of the start address of the TCB 212 of the second task which is the head of the matrix.
The content of the task connection pointer of the TCB 212 of the second task is 00 (hexadecimal representation) to indicate the lower 8 bits of the start address of the TCB 213 of the first task. The contents of the task connection pointer of the TCB 213 of the first task are 0E (hexadecimal notation) to indicate the lower 8 bits of the start address of the TCB 214 of the third task. The contents of the task connection pointer of TCB 214 of the third task contain a special code (
For example, it is FF (hexadecimal notation).

In this way, a queue is constructed by sequentially pointing to the lower 8 bits of the start address of each TCB.

FIG. 3 is a flowchart showing the processing of the TCB placement means 2 in FIG. In FIG. 3, step 30
1 reads a page address as a placement page (7 in this case), and sets the initial value of the TCB placement address and task count value N from the TCB initialization information file. Step 302 reads the initialization information of the Nth TCB, step 303 generates a TCB, and step 304 places the generated TCB in order from the placement address. Step 305 contrasts the next TCB by moving the placement address by the size of the TCB for the next TCB and increasing N by one. Step 3
06 looks at the next TCB initialization information and determines whether there are any more tasks. If there are, the process proceeds to step 302; if not, the process ends.

FIG. 4 is a flow diagram showing the processing of the task connection management means 5 of FIG. In FIG. 4, step 4
01 reads the connection queue 7 in FIG. 1 and performs step 4.
In step 11, a page address is set in the upper 8 bits of the address, and in step 402, the data read in step 401 is used as TCB address information. In step 403, it is determined whether or not there is a TCB to be connected next. If there is, the process goes to the next step 404, and if there is not, the TCB is connected in step 405. In step 404, the task connection pointer of the TCB at the indicated address is read, and the process returns to step 402.

In this embodiment, the initial value of the TCB placement address is set to 0, but the initial value may be anywhere from 0 to 255 as long as the TCB is placed at addresses 0 to 255.

FIG. 5 shows a second embodiment (claim 2) of the present invention.
FIG. 2 is a functional block diagram showing the configuration of a multitask control device in FIG.

The difference from the first embodiment is a placement start address detection means 509 that detects and outputs the TCB placement start address from the TCB placement means 502, and a placement end that detects and outputs the TCB placement end address. The difference is that an address detection means 519, a layout address determination means 510 for determining whether these two addresses exist on the same page, and a warning means 511 for outputting an error based on the determination result are provided.

The operation of the multitask control device of this embodiment configured as described above will be explained below with reference to FIG.

The placement start address detection means 509 is the TCB
The placement means 502 detects and outputs the placement start address when the TCB placement starts, and the placement end address detection means 519 detects and outputs the placement end address when the TCB placement means 502 completes the TCB placement. do. The arrangement address determination means 510 determines that these two addresses are 256
It is determined whether they exist on the same page of the memory where bytes are managed as one page, and if they are not on the same page, the warning means 511
prints an error and issues a warning.

[0046]

[Effects of the Invention] As explained above, according to the present invention,
page input means for inputting a page address for arranging the TCB;
A means for arranging a task control block in a specified page address space, and a task connection instructing means and a task head instructing means for connecting a task using a lower 8-bit address on the premise that the management address is from address 0 to address 255. By providing this, the task connection instruction means and the task start instruction means only need to save the lower 8 bits of the instruction address, which not only makes it possible to reduce the memory area used, but also allows Since the microprocessor of the bus can refer to the address of the next connected TCB by performing one memory access, the task connection management means can perform task connection processing at high speed.

Furthermore, by providing a warning means that warns when the arrangement address exceeds 255 when the TCB is arranged, malfunctions of the multitasking control device can be known in advance.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing the configuration of a multitask control device in a first embodiment of the present invention.

FIG. 2 (a) is a TCB configuration diagram showing an example of the configuration of a task control block in the first embodiment; (b) is a TCB configuration diagram showing an example of the configuration of a task control block in the first embodiment; Task connection diagram

[Fig. 3] Flow diagram showing the contents of processing by the TCB placement means in the same embodiment.

FIG. 4 is a flow diagram showing the processing procedure of the task connection management means in the same embodiment.

FIG. 5 is a functional block diagram showing the configuration of a multitask control device in a second embodiment of the present invention.

[Fig. 6] Functional block diagram showing the configuration of a conventional multitask control device

[Figure 7] (a) is a TCB configuration diagram showing one configuration example of a conventional task control block; (b) is a task connection diagram when a queue is configured by connecting conventional task control blocks;

[Fig. 8] Flow diagram showing the processing contents of the conventional TCB placement means

FIG. 9 is a flow diagram showing an example of a processing procedure of a conventional task connection management means.

[Explanation of symbols]

1 TCB initialization information 2 TCB arrangement means 3. Memory 4,213 TCB of 1st task 5,212 Second task TCB 6,214 Third task TCB 7,211 Connection queue 8 Task connection management means 11 Page input means 201 Task connection pointer

Claims (2)

[Claims] 1. N task control blocks that store task management information necessary for switching and executing a plurality of tasks; and memory means that can write and read arbitrary information by specifying a management address; The memory page at the address where the N task control blocks are placed is 256.
a page input means for specifying a byte as one page; and a predetermined setting such that the N task control blocks are entered at management addresses 0 to 255 within page 1 of the memory input from the page input means of the memory means. a task control block arrangement means for arranging the task control block in the address space of the N task control blocks, and a task control block arrangement address of the next task to be connected in order to configure a queue of a plurality of tasks, which is included in each of the N task control blocks. N task connection instruction means for storing lower 8 bits of information and indicating task connections;
A multi-task control device comprising: task header indicating means for storing lower 8 bits of placement address information of a task control block of the task in order to indicate the header task of the queued tasks. 2. N task control blocks that store task management information necessary for switching and executing a plurality of tasks; and memory means that can write and read arbitrary information by specifying a management address; The memory page at the address where the N task control blocks are placed is 256.
a page input means for specifying a byte as one page; and a predetermined setting such that the N task control blocks are entered at management addresses 0 to 255 within page 1 of the memory inputted from the page input means of the memory means. task control block placement means for placing the task control block in an address space; placement start address detection means for detecting address information at the beginning of the N task control blocks; and detection means for detecting address information at the end of the N task control blocks. an arrangement end address detection means for detecting the arrangement end address, an address determination means for determining whether two addresses detected by the arrangement start address detection means and the arrangement end address detection means are on the same page, and a result of the address comparison means A multi-task control device comprising: warning issuing means for issuing a warning if the number is 256 or more.