JPH0432479B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention shares memory by providing multiple access ports and enabling multiple data reads and multiple data writes at the same time. The present invention relates to a multiport memory that increases the shared memory access speed of a multiprocessor system consisting of a plurality of processors.

(Prior Art) As processing demands on computer systems have become more complex and sophisticated, expectations are increasing for parallel processing using multiprocessor systems that have multiple processors, which are the processing core of computer systems. . There is a method of using a shared memory as a means of transmitting information between processors in this multiprocessor system. One way to implement shared memory that is accessed by multiple processors is to connect the multiple processors and shared memory that make up the multiprocessor system via a bus, and to use dedicated hardware (arbiter) that arbitrates the right to use the bus. There is a bus coupling method to use.

(Problem to be Solved by the Invention) In a shared memory using the conventional bus coupling method, an arbiter that arbitrates the right to use the bus determines one processor to access the shared memory, thereby controlling access to the shared memory. This solved the problem of competing for shared memory between multiple desired processors. That is, the arbiter arbitrates shared memory access rights, thereby sequentially processing shared memory access requests from a plurality of processors. Therefore, as the number of processors that make up a multiprocessor system increases, the frequency of access to shared memory increases. The problem was that the effects of multiple parallel processing could not be fully utilized.

An object of the present invention is to replace shared memory access, which was processed sequentially in the prior art, by providing multiple access ports and making it possible to read multiple data and write multiple data at the same time. The objective is to provide a multiport memory that can process accesses in parallel.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the multiport memory provided by the present invention is provided with a plurality of input/output shared access ports, and has the same number of rows as the number of said access ports. memories of the square of the number of said access ports arranged in a grid of columns;
The latest data is selected from the output data of the memory of the same number as the number of the access ports arranged on the two columns, and the latest data is output to the access ports. It consists of a control multi-port memory that stores access port numbers and controls the selector when reading data.The access cycle consists of a data read phase and a data write phase, and in the data read phase, addresses and giving the number of the access port that performed the writing output by the control multiport memory;
The selector selects the output of the memory storing the latest data according to the access port number output by the control multiport memory, and in the data write phase, it gives an address for each row and writes all the data belonging to that row. By writing data to the memory and at the same time storing the access port number used for writing in the control multi-port memory,
If the total number of data to be accessed during one access cycle is less than or equal to the number of access ports,
It is characterized by being able to read any number of data and write any number of data.

(Operation) The multi-port memory of the present invention is configured with the square of the number of access ports. Multi-port of the present invention when there are four access ports
Explain memory. FIG. 2 is a block diagram of the data bus system of the multiport memory of the present invention. 16 memories are arranged in a grid of 4 rows and 4 columns. The rows are 1, 2, 3, 4 from bottom to top.
and number them. 200, 201, 202, 20
3 is a memory forming the first row. This memory may be a conventional random access memory. Therefore, it is also possible to use a 1 megabit random access memory to realize a multi-port memory with a large capacity of several megawords.
The columns are numbered 1, 2, 3, 4 from left to right. Memories 200, 210, 220, and 230 constitute the first column. The four memories arranged in one row store the same data.
Four memories arranged in one column are assigned to each access port. Each column contains the 4 that belong to the column.
selectors 250, 251 for selecting data to be output to the access port from the output data of the memories;
There are 252,253. Selectors 250, 251,
252 and 253 select a memory at the output of a 2-bit wide control 4-port memory 260. The control 4-port memory stores the number of the memory storing valid data at each address.

The operating principle of the multi-port memory of the present invention will be explained using an example of a data access operation. First, an example of a write operation using access port 2 will be explained. The write data is "3". FIG. 3 shows the contents of the memory section at the address where the write operation is to be performed and the initial state of the four access ports of the four-port control memory. Control 4-port memory access port 372 and third column memory 30
2, 312, 322, and 332 output the contents of the write address. At this time, the memory 300 of the other row,
301, 302, 303, 310, 312, 31
3, 330, 331, 332, 333 and control 4
Other access ports 37 of port memory 360
0, 371, and 373 may be used for write operations to addresses other than those targeted by the write operation sequence. However, to make it easier to understand the operating principle,
Indicates the contents of the write address in all memory locations.
320, 321, 322, and 323 are the initial states of the four memories in the third row that the access port 2 uses for writing. The access cycle consists of two phases, and the write operation is performed in the second phase. The first phase performs a read operation that will be explained later. A write operation is performed on the four memories 32 in the third row.
Write data “3” to the write addresses 0, 321, 322, and 323, and then write the write data “3” to the write addresses 0, 321, 322, and 323, and then write the write data “3” to the write addresses 0, 321, 322, and 323, and
Access port number “2” used for writing to
Write. FIG. 4 shows the state after the write operation is completed. Similarly to Figure 3, in the 16 memory locations,
Indicates the contents of the write address. The contents of the write address are also shown at the access port 472 of the control 4-port memory 460. Memories 420, 421, 42 belonging to the third row in which data was written
The content of the write address 2,423 is "3", and the access port 47 of the 4-port control memory 460
The contents of the write address output by 2 have been rewritten to "2". The content "2" of the address written in the control 4-port memory indicates that valid data at this address exists in the third row of memory.

Next, a read operation using access port 2 will be explained. The read address is the address used in the explanation of the write operation. FIG. 5 shows the state of the memory section at the address and the control 4-port memory after the write operation. 502, 512, 522, and 532 are the contents of four memories belonging to the third column used by the access port 2. A read operation is performed in the first phase. The second phase may be used for write operations at other addresses. In the first phase, four memories 502, 512, 52 belonging to the third column
2,532 and the contents of the read address of the second access port 572 of the four-port control memory. Memories of other columns 500, 510, 520,
530, 501, 511, 521, 531, 50
3,513,523,533 and 4 ports for control.
Other access ports 570, 57 of memory 560
1,573 may be used for read operations to addresses other than the example used in the explanation. The output "2" of the access port 572 of the control 4-port memory 560 controls the selector 552 assigned to the third column. The selector 552 selects the memory 502 if the output of the access port 572 of the control 4-port memory 560 is "0", and selects the memory 51 if the output is "1".
2. If the value is "2", the memory 522 is selected; if the value is "3", the memory 532 is selected. access port 572
Since the output of is "2", the output of memory 522 is selected as the output of access port 2. The memory 522 is outputting the value "3" written earlier.

As a result, if the access cycle of the multi-port memory of the present invention is made into two phases, a data read phase and a data write phase, if the number of data to be accessed is less than or equal to the number of access ports, multiple data can be read and Multiple pieces of data can be written in one access cycle.

(Example) Examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the multiport memory of the present invention in which the number of access ports is four.

It consists of a memory unit 100 for storing data and a control 4-port memory 101 for specifying the memory to be accessed in a read operation. The memory unit 100 is
Memories 110 and 11 arranged in a grid of 4 rows and 4 columns
1,112,113,120,121,122,
123, 130, 131, 132, 133, 14
0, 141, 142, 143 and selectors 150, 151, 152, 153 for selecting the output of the memory to be output to the access port in a read operation. For the memories 110 to 143, if a dynamic memory refresh function is provided, a 1 megabit dynamic memory can be used, and a large capacity multi-port memory can be realized. The operation will be explained using a data read operation using the access port 105 as an example. In the first phase (data read phase) of the access cycle, the read address of the access port 105 is sent to the four access ports 160, 161, 162, 163 of the control four-port memory 101 and the four memories in each column. It will be done. The notification of the read address is shown in the first
The access port 105 will be explained as an example. Using the read address of the first access port 105,
The memory number storing valid data is read from the access port 160 of the 4-port control memory 101. At the same time, access port 105
The read address of selectors 170, 180, 19
0, memory 110, 120, 130, 14
Go to 0. Memory 110, 120, 130, 14
0 outputs the contents of the given read address. The selector 150 is a control 4-port memory 1
According to the output of the access port 160 of No. 01, data to be output to the access port 105 is selected from the outputs of the four memories. This completes the read operation.

Next, the operation will be explained using a data write operation using the access port 105 as an example. Second phase of access cycle (data write phase)
Then, the write address of each access port is sent to the four access ports of the control 4-port memory 101 and the four memories in each row. The manner in which the write address is notified will be explained using the first access port 105 as an example. The write address of the access port 105 is selected by the selectors 171, 172, 173, and the access port 1 of the memories 110, 111, 112, 113 in the first row and the 4-port control memory 101 is selected by the selectors 171, 172, 173.
Sent to 01. And access port 105
The write data of the memory 110, 111, 11
2,113. At the same time, the output of the register 165 storing the access port number "0" is written to the access port 160 of the control 4-port memory 101. This completes the write operation.

(Effects of the Invention) The multi-port memory of the present invention includes memories of the square of the number of access ports arranged in a lattice pattern and a multi-port memory with a small data width that stores the number of the access port used for data writing. and divides the access cycle into a read phase and a write phase, characterized in that in the read phase each access port uses memory belonging to a specific column, and in the write phase each access port uses memory belonging to a specific row. shall be. As a result, if the number of data to be accessed is less than or equal to the number of access ports, a multi-port memory with a large data width can be used to read any number of data and write any number of data in one access cycle. It has been realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a multi-port memory of the present invention when there are four access ports, and FIGS. 2 to 5 are diagrams for explaining the operation of the present invention. In the figure, 100 is a memory section, 101 is a 4-port memory for control, 105, 106, 107,
108 is an access port of this multiport memory, 110, 111, 112, 113, 120,
121, 122, 123, 130, 131, 13
2, 133, 140, 141, 142, 143 are memories, 150, 151, 152, 153 are read data selectors, 160, 161, 162,
163 is an access port of the control 4-port memory; 165, 166, 167, 168 are registers that store access port numbers; 170, 17
1,172,173,180,181,182,
183, 190, 191, 192, and 193 are selectors for selecting memory addresses.

Claims (1)

[Claims] 1. A memory having a plurality of input/output shared access ports and arranged in a grid having the same number of rows and columns as the number of access ports, the square of the number of the access ports, and a memory arranged on one column. The latest data is selected from the output data of the memory of the same number as the number of the access ports, and a selector provided for each column to be output to the access port and the number of the access port used at the time of data writing are memorized. , a control multi-port memory that controls the selector when reading data;
The access cycle consists of a data read phase and a data write phase, and in the data read phase, the address and the number of the access port that performed the write output from the control multiport memory are given for each column, and the selector Select the output of the memory that stores the latest data according to the access port number output by the multi-port memory, and in the data write phase, give an address for each row, write data to all memories belonging to that row, and write the data at the same time. By recording the access port number used for writing in the control multiport memory, any number of data can be accessed during one access cycle as long as the total number of data to be accessed is less than or equal to the number of access ports. A multi-port memory characterized by being able to read and write any number of data.