JPH04326830A - Transmission line selecting system - Google Patents

Transmission line selecting system

Info

Publication number
JPH04326830A
JPH04326830A JP3123091A JP12309191A JPH04326830A JP H04326830 A JPH04326830 A JP H04326830A JP 3123091 A JP3123091 A JP 3123091A JP 12309191 A JP12309191 A JP 12309191A JP H04326830 A JPH04326830 A JP H04326830A
Authority
JP
Japan
Prior art keywords
clock
transmission path
phase
transmission line
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3123091A
Other languages
Japanese (ja)
Inventor
Ryoichi Ekusa
了一 江草
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3123091A priority Critical patent/JPH04326830A/en
Publication of JPH04326830A publication Critical patent/JPH04326830A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Selective Calling Equipment (AREA)

Abstract

PURPOSE:To switch a transmission line before a fault when there is any trouble in the accuracy of a clock frequency on the transmission line at a circuit to generate a clock synchronizing the phase to that of a clock extracted from the transmission line. CONSTITUTION:A synchronizing clock (b) is generated from a phase-locked clock oscillation circuit 2 to input a clock (a) extracted from the transmission line. The frequency of this synchronized clock is measured by a high-speed and high-accuracy clock. According to this measured result, the accuracy of the clock on the transmission line is judged, and the transmission line is switched. Thus, the fault caused by the abnormality of the clock accuracy on the transmission line can be prevented in advance.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、伝送路から抽出される
クロック信号に位相同期したクロック信号を発振する位
相同期発振回路の伝送路選択方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission path selection method for a phase-locked oscillator circuit that oscillates a clock signal phase-synchronized with a clock signal extracted from a transmission path.

【0002】0002

【従来の技術】従来、伝送路の選択方式は伝送路上のク
ロック周波数精度が問われることが無く、クロック信号
自体の途絶あるいは位相同期発振回路での位相同期不能
な状態が発生するまで伝送路を切り替えることはなかっ
た。
[Prior Art] Conventionally, in the transmission path selection method, the accuracy of the clock frequency on the transmission path is not questioned, and the transmission path is continued until the clock signal itself is interrupted or a state in which phase synchronization is not possible in the phase synchronized oscillator circuit occurs. There was no switching.

【0003】0003

【発明が解決しようとする課題】前述した従来の伝送路
選択方式では、位相同期発振回路がクロックを供給して
いる装置の不具合原因が伝送路上のクロック周波数精度
にある場合、これを特定できる監視手段を持っていなか
った。
[Problems to be Solved by the Invention] In the conventional transmission path selection method described above, if the cause of a malfunction in the device to which the phase synchronized oscillation circuit supplies clocks is due to the clock frequency accuracy on the transmission path, monitoring is required to identify this problem. I didn't have the means.

【0004】本発明の目的は、このような問題点を解決
した伝送路選択方式を提供することにある。
[0004] An object of the present invention is to provide a transmission path selection system that solves these problems.

【0005】[0005]

【課題を解決するための手段】上記の問題点を解決する
ために、本発明の伝送路選択方式は、伝送路から抽出し
たクロック信号に位相同期したクロックを出力する位相
同期クロック発振回路において、位相同期クロック発振
回路にて生成した同期クロックを高速かつ高精度のクロ
ック信号を用いて周波数測定する手段と、前記周波数測
定結果より伝送路のクロック精度を判断し伝送路切り替
え制御を行う手段とを有する。
[Means for Solving the Problems] In order to solve the above-mentioned problems, the transmission line selection method of the present invention provides a phase-synchronized clock oscillator circuit that outputs a clock that is phase-synchronized with a clock signal extracted from a transmission line. A means for measuring the frequency of a synchronized clock generated by a phase synchronized clock oscillator circuit using a high-speed and high-precision clock signal, and a means for determining the clock accuracy of a transmission line from the frequency measurement result and controlling transmission line switching. have

【0006】また本発明の伝送路選択方式は、複数の伝
送路の選択切り替えを行うと共にクロック信号を抽出す
る伝送路選択器と、この伝送路選択器が選択した伝送路
から抽出したクロック信号に位相同期したクロックを出
力する位相同期クロック発振器と、この位相同期クロッ
ク発振器にて生成した同期クロックを高速かつ高精度の
クロック信号を用いて周波数測定する周波数測定器と、
周波数測定結果より伝送路のクロック精度を判断し前記
伝送路選択器に対して伝送路切り替え制御を行う演算処
理装置とを有することを特徴とする。
The transmission path selection method of the present invention also includes a transmission path selector that selects and switches between a plurality of transmission paths and extracts a clock signal, and a clock signal that is extracted from the transmission path selected by the transmission path selector. a phase-synchronized clock oscillator that outputs a phase-synchronized clock; a frequency measuring device that measures the frequency of the synchronized clock generated by the phase-synchronized clock oscillator using a high-speed and high-precision clock signal;
The present invention is characterized by comprising an arithmetic processing unit that determines the clock accuracy of the transmission line from the frequency measurement result and controls the transmission line switching for the transmission line selector.

【0007】[0007]

【実施例】本発明の実施例について図面を参照して説明
する。
Embodiments Examples of the present invention will be described with reference to the drawings.

【0008】図1は本発明の一実施例を示す図である。 この伝送路選択方式は、伝送路選択器1と、位相同期ク
ロック発振器(PLO)2と、高速クロック発振器3と
、周波数測定器4と、演算処理装置5とを備えている。
FIG. 1 is a diagram showing an embodiment of the present invention. This transmission path selection system includes a transmission path selector 1, a phase-locked clock oscillator (PLO) 2, a high-speed clock oscillator 3, a frequency measuring device 4, and an arithmetic processing unit 5.

【0009】伝送路選択器1は、複数本の伝送路(1〜
n)から1本の伝送路を選択すると共に、クロック信号
を抽出する。
The transmission path selector 1 selects a plurality of transmission paths (1 to 1).
Select one transmission line from n) and extract the clock signal.

【0010】位相同期クロック発振器2は、伝送路選択
器1が選択した伝送路から抽出したクロック信号に位相
同期したクロックを出力する。
The phase synchronized clock oscillator 2 outputs a clock that is phase synchronized with the clock signal extracted from the transmission path selected by the transmission path selector 1.

【0011】高速クロック発振器3は、高速かつ高精度
のクロックを発生し、周波数測定器4に出力する。
[0011] The high-speed clock oscillator 3 generates a high-speed and highly accurate clock and outputs it to the frequency measuring device 4.

【0012】周波数測定器4は、位相同期クロック発振
器2の発生するクロック発振器の周波数を、高速かつ高
精度のクロックを用いて測定する。
The frequency measuring device 4 measures the frequency of the clock oscillator generated by the phase synchronized clock oscillator 2 using a high-speed and highly accurate clock.

【0013】演算処理装置5は、周波数測定結果により
伝送路のクロック精度を判断し伝送路選択器1に対して
伝送路切り替え制御を行う。
The arithmetic processing unit 5 determines the clock accuracy of the transmission line based on the frequency measurement result and controls the transmission line selector 1 to switch the transmission line.

【0014】次に、本実施例の動作を説明する。Next, the operation of this embodiment will be explained.

【0015】伝送路から伝送路選択器1を経由して抽出
された抽出クロック信号aを入力とする位相同期クロッ
ク発振器2の出力の同期クロック信号bは他回路に対し
出力されると共に、周波数測定器4に入力される。周波
数測定器4は、図2に示すように、位相同期クロック発
振器の出力クロック(同期クロック信号)bが一定のク
ロック数だけカウントされる期間内に高速クロック発振
器3の出力クロック(高速クロック)が何個含まれてい
るかをカウントし、このカウント数より周波数測定をす
る。周波数測定は周期的に行い、測定結果を演算処理装
置5に出力する。演算処理装置5は入力される周波数測
定結果が設定されているしきい値を越えた場合に伝送路
選択器1を制御することにより抽出クロック信号aを得
る伝送路の切り替えを行う。
The synchronized clock signal b output from the phase synchronized clock oscillator 2 which receives the extracted clock signal a extracted from the transmission path via the transmission path selector 1 is outputted to other circuits, and is also used for frequency measurement. The signal is input to device 4. As shown in FIG. 2, the frequency measuring device 4 measures the output clock (high-speed clock) of the high-speed clock oscillator 3 within a period in which the output clock (synchronous clock signal) b of the phase synchronized clock oscillator is counted by a certain number of clocks. Count how many are included and measure the frequency based on this count. Frequency measurement is performed periodically and the measurement results are output to the arithmetic processing unit 5. When the input frequency measurement result exceeds a set threshold value, the arithmetic processing unit 5 controls the transmission path selector 1 to switch the transmission path for obtaining the extracted clock signal a.

【0016】[0016]

【発明の効果】以上説明したように本発明は、位相同期
クロック発振器出力の発振周波数を測定することによっ
て伝送路のクロック精度異常を検出することができ、測
定結果を用いて抽出クロックを得る伝送路の切り替えを
行うことにより、他装置において障害が発生する以前に
伝送路切り替えを行うことができる効果がある。
As explained above, the present invention can detect an abnormality in the clock accuracy of a transmission line by measuring the oscillation frequency of the output of a phase synchronized clock oscillator, and uses the measurement results to obtain an extracted clock. By switching the transmission path, it is possible to switch the transmission path before a failure occurs in another device.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.

【図2】図1の伝送路選択方式の動作タイミングを示す
図である。
FIG. 2 is a diagram showing the operation timing of the transmission path selection method in FIG. 1;

【符号の説明】[Explanation of symbols]

1  伝送路選択器 2  位相同期クロック発振器 3  高速クロック発振器 4  周波数測定器 5  演算処理装置 1 Transmission path selector 2 Phase synchronized clock oscillator 3 High-speed clock oscillator 4 Frequency measuring device 5 Arithmetic processing unit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】伝送路から抽出したクロック信号に位相同
期したクロックを出力する位相同期クロック発振回路に
おいて、位相同期クロック発振回路にて生成した同期ク
ロックを高速かつ高精度のクロック信号を用いて周波数
測定する手段と、前記周波数測定結果より伝送路のクロ
ック精度を判断し伝送路切り替え制御を行う手段とを有
することを特徴とする伝送路選択方式。
Claim 1: In a phase-synchronized clock oscillation circuit that outputs a clock that is phase-synchronized with a clock signal extracted from a transmission path, the synchronized clock generated by the phase-synchronized clock oscillation circuit is frequency-controlled using a high-speed and highly accurate clock signal. 1. A transmission path selection method comprising: a means for measuring the frequency; and a means for determining the clock accuracy of the transmission path based on the frequency measurement result and controlling transmission path switching.
【請求項2】複数の伝送路の選択切り替えを行うと共に
クロック信号を抽出する伝送路選択器と、この伝送路選
択器が選択した伝送路から抽出したクロック信号に位相
同期したクロックを出力する位相同期クロック発振器と
、この位相同期クロック発振器にて生成した同期クロッ
クを高速かつ高精度のクロック信号を用いて周波数測定
する周波数測定器と、周波数測定結果より伝送路のクロ
ック精度を判断し前記伝送路選択器に対して伝送路切り
替え制御を行う演算処理装置とを有することを特徴とす
る伝送路選択方式。
2. A transmission path selector that selects and switches between a plurality of transmission paths and extracts a clock signal, and a phase that outputs a clock whose phase is synchronized with the clock signal extracted from the transmission path selected by the transmission path selector. a synchronous clock oscillator; a frequency measuring device that measures the frequency of the synchronous clock generated by the phase synchronous clock oscillator using a high-speed and high-precision clock signal; 1. A transmission path selection method, comprising: an arithmetic processing unit that performs transmission path switching control on a selector.
JP3123091A 1991-04-26 1991-04-26 Transmission line selecting system Pending JPH04326830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3123091A JPH04326830A (en) 1991-04-26 1991-04-26 Transmission line selecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3123091A JPH04326830A (en) 1991-04-26 1991-04-26 Transmission line selecting system

Publications (1)

Publication Number Publication Date
JPH04326830A true JPH04326830A (en) 1992-11-16

Family

ID=14851985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3123091A Pending JPH04326830A (en) 1991-04-26 1991-04-26 Transmission line selecting system

Country Status (1)

Country Link
JP (1) JPH04326830A (en)

Similar Documents

Publication Publication Date Title
JP2620783B2 (en) Multi-channel tester synchronization circuit
KR100871205B1 (en) Multiple Clock Phase Determination System
EP1421397B1 (en) Delay fault test circuitry and related method
KR101795199B1 (en) Signal processing device
JPH04326830A (en) Transmission line selecting system
JPH0424667B2 (en)
US5796272A (en) Frequency deviation detection circuit
JP2819890B2 (en) Skew adjustment circuit
JP3536780B2 (en) Sync source signal switching circuit
JPH04178047A (en) Skew compensation system
KR100221496B1 (en) Synchronous state monitoring circuit
JPS6211181A (en) Tester for large-scale integrated circuit
JPH04168824A (en) Phase synchronizing oscillation circuit
JPH0567967A (en) Clock generator
KR920003362B1 (en) Method and an apparatus for compensating fine phase difference of clock signals
JPS585614B2 (en) phase synchronized oscillator
JP2599759B2 (en) Flip-flop test method
US6859912B2 (en) Method and circuit arrangement for clock recovery
KR200262927Y1 (en) Clock fail detector
JPS597974B2 (en) Synchronizer for loop transmission system
KR100333258B1 (en) Frequency control method of redundancy time / frequency generator
JP2004229020A (en) Automatic phase differential regulating system
JP2885494B2 (en) Clock pulse generation circuit
JPH08204553A (en) Abnormal clock detection circuit
JPH0451716A (en) Plo changeover circuit