JPH04329208A - Electrically conductive paste and mounting substrate using the same - Google Patents

Electrically conductive paste and mounting substrate using the same

Info

Publication number
JPH04329208A
JPH04329208A JP3100672A JP10067291A JPH04329208A JP H04329208 A JPH04329208 A JP H04329208A JP 3100672 A JP3100672 A JP 3100672A JP 10067291 A JP10067291 A JP 10067291A JP H04329208 A JPH04329208 A JP H04329208A
Authority
JP
Japan
Prior art keywords
conductive paste
conductive
paste according
electrically conductive
conductive filler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3100672A
Other languages
Japanese (ja)
Inventor
Akihito Hatakeyama
畠山 秋仁
Hirotoshi Watanabe
寛敏 渡辺
Yasuhiko Horio
泰彦 堀尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3100672A priority Critical patent/JPH04329208A/en
Publication of JPH04329208A publication Critical patent/JPH04329208A/en
Pending legal-status Critical Current

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  • Paints Or Removers (AREA)
  • Conductive Materials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To provide a highly reliable electric connection by using a non- hardenable electrically conductive paste, and thereby easing the stress attributable to the thermal stress generated at the time of, for example, cold/hot impact test. CONSTITUTION:The electrically conductive paste 1 comprises an electrically conductive filler for which an Ag powder (particle size: 0.2 to 9mum), an Ag-Pd alloy powder (particle size: 0.1 to 15mum), and an Au powder (particle size: 0.5 to 1.2mum) are used, and a binder for which a non-hardenable silicone resin and white petrolatum are used. When the content of the Ag powder is 90wt.%, the paste 1 exhibits a minimum volumetric resistirity almost independently of the kind of the binder.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、ICチップに代表され
るチップ状の電子部品を基板上の端子電極群と接続する
ために用いられる導電性ペースト、およびこれを用いた
実装基板に関するものである。
[Field of Industrial Application] The present invention relates to a conductive paste used for connecting chip-shaped electronic components such as IC chips to a group of terminal electrodes on a board, and a mounting board using the same. be.

【0002】0002

【従来の技術】従来、電子部品の接続端子と基板上の回
路パターン端子との接続には半田がよく利用されていた
が、近年、たとえばICフラットパッケージ等の小型化
と、接続端子間、いわゆるピッチ間隔が次第に狭くなり
、従来の半田付け技術で対処することが次第に困難にな
ってきた。
[Prior Art] In the past, solder was often used to connect the connection terminals of electronic components and the circuit pattern terminals on the board, but in recent years, with the miniaturization of IC flat packages, etc. The pitch spacing has become progressively narrower, making it increasingly difficult to address with traditional soldering techniques.

【0003】また、最近では電卓、電子時計あるいは液
晶ディスプレイなどにあっては、裸のICチップを基板
上の電極に直付けして実装面積の効率的利用を図ろうと
する動きがあり、有効かつ微細な電気的接続手段が強く
望まれている。裸のICチップを基板の電極と電気的に
接続する方法としては、ICチップの電極パッド上に形
成した突出接点(Auバンプ)と基板の端子電極群とを
熱硬化タイプの導電性ペーストを用いて接続する方法が
知られている。
[0003] Recently, there has also been a movement toward efficient use of mounting area by directly attaching bare IC chips to electrodes on substrates for calculators, electronic watches, and liquid crystal displays. Fine electrical connection means are strongly desired. A method for electrically connecting a bare IC chip to an electrode on a substrate is to connect the protruding contacts (Au bumps) formed on the electrode pads of the IC chip and the terminal electrode group on the substrate using a thermosetting conductive paste. There are known methods for connecting.

【0004】0004

【発明が解決しようとする課題】しかしながら従来の熱
硬化タイプの導電性ペーストではICチップと回路基板
との熱膨張係数が異なるため熱ストレスによる応力によ
って接続部の劣化が生じやすいという問題があった。
[Problems to be Solved by the Invention] However, with conventional thermosetting conductive pastes, there was a problem in that the thermal expansion coefficients of the IC chip and the circuit board were different, so that the connection parts were likely to deteriorate due to stress caused by thermal stress. .

【0005】本発明は上記問題点に鑑みてなされたもの
であり、その目的とするところは、電子部品の電極パッ
ドと基板上の電極群との接続に際して熱ストレスによる
応力を緩和することが可能な導電性ペーストを得ること
およびこれを用いて信頼性の高い実装基板を得ることに
ある。
The present invention has been made in view of the above problems, and its purpose is to alleviate stress caused by thermal stress when connecting an electrode pad of an electronic component to an electrode group on a substrate. The object of the present invention is to obtain a conductive paste and to obtain a highly reliable mounting board using the same.

【0006】[0006]

【課題を解決するための手段】本発明は上記問題点を解
決するため、液状の樹脂、ゲルを用いて応力緩和が可能
な非硬化性の導電性接着剤を実現し、ICチップと回路
基板の端子電極との電気的接続において前記非硬化性の
導電性ペーストを用いて熱ストレスによる応力の緩和を
実現しようとするものである。
[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention realizes a non-hardening conductive adhesive capable of stress relaxation using liquid resin or gel, and uses it to bond IC chips and circuit boards. The present invention attempts to alleviate stress caused by thermal stress by using the non-hardening conductive paste in electrical connection with terminal electrodes.

【0007】[0007]

【作用】本発明の上記した方法によれば、非硬化性の導
電性ペーストを用いることにより冷熱衝撃試験などで生
じる熱ストレスによる応力を緩和することができ、信頼
性の高い電気的接続を図れる。
[Operation] According to the above-described method of the present invention, by using a non-hardening conductive paste, it is possible to alleviate stress caused by thermal stress caused by a thermal shock test, etc., and a highly reliable electrical connection can be achieved. .

【0008】[0008]

【実施例】以下、本発明の一実施例の導電性ペーストと
これを用いた実装基板について図面に基づき詳細に説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A conductive paste according to an embodiment of the present invention and a mounting board using the same will be described in detail below with reference to the drawings.

【0009】図1は本発明の導電性ペーストを用いた実
装基板の構造断面図である。図1において1は導電性ペ
ースト、2はICチップ、3はICチップの電極パッド
、4はAuバンプ(突出接点)、5はAu厚膜電極、6
はガラス基板である。
FIG. 1 is a structural sectional view of a mounting board using the conductive paste of the present invention. In FIG. 1, 1 is a conductive paste, 2 is an IC chip, 3 is an electrode pad of the IC chip, 4 is an Au bump (protruding contact), 5 is an Au thick film electrode, and 6
is a glass substrate.

【0010】本発明の実施例では、導電性ペースト1と
して導電性フィラーにAg粉体(粒度0.2〜9μm)
、AgPd合金粉体(粒度0.1〜15μm)、Au粉
体(粒度0.5〜1.2μm)、バインダーに非硬化性
シリコーンレジン(東レ・シリコーン(株)製)、白色
ワセリン(ナカライテスク(株)製)を用いて作製した
ものを使用した。Ag粉体の含有量が90重量%のとき
導電性ペーストはバインダーの種類にほとんど依存する
ことなくその体制抵抗率は最小となる。
In the embodiment of the present invention, Ag powder (particle size 0.2 to 9 μm) is added to the conductive filler as the conductive paste 1.
, AgPd alloy powder (particle size 0.1 to 15 μm), Au powder (particle size 0.5 to 1.2 μm), non-hardening silicone resin (manufactured by Toray Silicone Co., Ltd.) as a binder, and white petrolatum (Nacalai Tesque). (manufactured by Co., Ltd.) was used. When the content of Ag powder is 90% by weight, the conductive paste has a minimum systematic resistivity, almost independent of the type of binder.

【0011】AgPd合金粉末、Au粉末についてはそ
れぞれ93重量%、97重量%のとき導電性ペーストの
体積抵抗率は最小となる。導電性ペースト1をAuバン
プ4を施されたICチップ2に転写し、Auバンプ4を
導電性ペースト1を介してガラス基板6上のAu厚膜電
極5に接続する。このとき接着強度を補うためにICチ
ップ2を封止剤で覆うことも可能である。
For AgPd alloy powder and Au powder, the volume resistivity of the conductive paste is at its minimum when the content is 93% by weight and 97% by weight, respectively. The conductive paste 1 is transferred onto the IC chip 2 provided with the Au bumps 4, and the Au bumps 4 are connected to the Au thick film electrodes 5 on the glass substrate 6 via the conductive paste 1. At this time, it is also possible to cover the IC chip 2 with a sealant to supplement the adhesive strength.

【0012】従来との比較のためにバインダーとしてエ
ポキシ樹脂用いて実装基板を作製した。以上のようにし
て作製した実装基板に対しー40℃/30分〜+125
℃30分の熱ストレスを与えたときのICチップ2とA
u厚膜電極5間の抵抗値の初期値と抵抗値が10倍以上
になる回数を(表1)に示した。
For comparison with the conventional method, a mounting board was prepared using epoxy resin as a binder. -40℃/30 minutes to +125℃ for the mounting board prepared as above.
IC chips 2 and A when subjected to heat stress for 30 minutes at ℃
Table 1 shows the initial value of the resistance value between the u-thick film electrodes 5 and the number of times the resistance value becomes 10 times or more.

【0013】[0013]

【表1】[Table 1]

【0014】本発明における非硬化性の導電性ペースト
と従来の熱硬化性の導電性ペーストを比較すると2〜5
倍の寿命延長が認められる。
Comparing the non-hardening conductive paste of the present invention with the conventional thermosetting conductive paste, the difference is 2 to 5.
The lifespan is doubled.

【0015】尚、本実施例では導電性フィラーとしてA
g、AgPd、Au粉体について述べたがその限りでは
なく、AgAu混合粉体の使用も可能である。また、他
の実施例としてチップ状の電子部品についてもICチッ
プと同様の効果が得らる。
In this example, A is used as the conductive filler.
Although the above description has been made of powders of Ag, AgPd, and Au, the present invention is not limited thereto, and it is also possible to use AgAu mixed powder. Further, as another example, the same effect as that of an IC chip can be obtained with a chip-shaped electronic component.

【0016】[0016]

【発明の効果】以上に説明したように、本発明の導電性
ペーストを用いれば熱ストレスによる応力の緩和に優れ
たICチップと基板との接続を行なうことが可能である
。また、本発明の導電性ペーストは硬化処理を必要とし
ないため実装工程を簡略化出来きる、さらにICチップ
のリペア性にも優れている。
As described above, by using the conductive paste of the present invention, it is possible to connect an IC chip and a substrate with excellent relaxation of stress caused by thermal stress. Further, since the conductive paste of the present invention does not require curing treatment, the mounting process can be simplified, and furthermore, it is excellent in repairability of IC chips.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第1の一実施例を示す構造断面図FIG. 1 is a structural sectional view showing a first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1  導電性ペースト 2  ICチップ 3  ICチップの電極パッド 4  Auバンプ(突出電極) 5  Au厚膜電極 6  ガラス基板 1 Conductive paste 2 IC chip 3 IC chip electrode pad 4 Au bump (protruding electrode) 5 Au thick film electrode 6 Glass substrate

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】  導電性フィラーとバインダーとからな
り、加熱によって硬化しないことを特徴とする導電性ペ
ースト。
1. A conductive paste comprising a conductive filler and a binder, which does not harden by heating.
【請求項2】  バインダーが液状あるいはゲル状シリ
コーン、ワセリン等の脂肪族炭化水素系の半固形の樹脂
の少なくとも1種以上からなることを特徴とする請求項
1記載の導電性ペースト。
2. The conductive paste according to claim 1, wherein the binder comprises at least one of liquid or gel silicone and aliphatic hydrocarbon semisolid resin such as vaseline.
【請求項3】  導電性フィラーがAg、Pd、Auの
少なくとも1種以上からなることを特徴とする請求項1
または2のいずれかに記載の導電性ペースト。
3. Claim 1, wherein the conductive filler is made of at least one of Ag, Pd, and Au.
or 2. The conductive paste according to any one of 2.
【請求項4】  導電性フィラーの粒度分布が15μm
以下であることを特徴とする請求項3に記載の導電性ペ
ースト。
[Claim 4] The particle size distribution of the conductive filler is 15 μm.
The conductive paste according to claim 3, characterized in that:
【請求項5】  導電性フィラーがAgからなることを
特徴とする請求項1または2のいずれかに記載の導電性
ペースト。
5. The conductive paste according to claim 1, wherein the conductive filler is made of Ag.
【請求項6】  導電性フィラーがAuからなることを
特徴とする請求項1または2のいずれかに記載の導電性
ペースト。
6. The conductive paste according to claim 1, wherein the conductive filler is made of Au.
【請求項7】  導電性フィラーがAgとPdの合金か
らなりAgが少なくとも70重量%以上含有することを
特徴とする請求項1または2のいずれかに記載の導電性
ペースト。
7. The conductive paste according to claim 1, wherein the conductive filler is made of an alloy of Ag and Pd and contains at least 70% by weight of Ag.
【請求項8】  最小の体積抵抗率を示す導電性フィラ
ーの含有量以上の導電性フィラーを含有することを特徴
とする請求項1または2のいずれかに記載の導電性ペー
スト。
8. The conductive paste according to claim 1, wherein the conductive paste contains a conductive filler in an amount equal to or more than the conductive filler exhibiting the minimum volume resistivity.
【請求項9】  バインダーが液状のシリコーンで、そ
の粘度が0.7〜5Pa・sであることを特徴とする請
求項4に記載の導電性ペースト。
9. The conductive paste according to claim 4, wherein the binder is liquid silicone and has a viscosity of 0.7 to 5 Pa·s.
【請求項10】  チップ状の電子部品の電極パッド上
に形成した突出接点と回路基板上の端子電極とを非硬化
性の導電性ペーストにより接続することを特徴とする実
装基板。
10. A mounting board characterized in that a protruding contact formed on an electrode pad of a chip-shaped electronic component and a terminal electrode on a circuit board are connected by a non-hardening conductive paste.
【請求項11】  チップ状の電子部品の電極パッドと
回路基板上の端子電極とを非硬化性の導電性ペーストに
より接続することを特徴とする実装基板。
11. A mounting board characterized in that an electrode pad of a chip-shaped electronic component and a terminal electrode on a circuit board are connected by a non-hardening conductive paste.
JP3100672A 1991-05-02 1991-05-02 Electrically conductive paste and mounting substrate using the same Pending JPH04329208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3100672A JPH04329208A (en) 1991-05-02 1991-05-02 Electrically conductive paste and mounting substrate using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3100672A JPH04329208A (en) 1991-05-02 1991-05-02 Electrically conductive paste and mounting substrate using the same

Publications (1)

Publication Number Publication Date
JPH04329208A true JPH04329208A (en) 1992-11-18

Family

ID=14280258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3100672A Pending JPH04329208A (en) 1991-05-02 1991-05-02 Electrically conductive paste and mounting substrate using the same

Country Status (1)

Country Link
JP (1) JPH04329208A (en)

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