JPH0433368A - Gate array semiconductor device - Google Patents

Abstract

PURPOSE:To improve the efficiency of power supply lines and facilitate design of wiring layout of signal lines, etc., by a method wherein a functional circuit is divided into a plurality of macro-cells and power supply terminals are provided on the respective macro-cells and then respective power supply lines are connected to the respective power supply terminals. CONSTITUTION:A functional circuit is divided into a plurality of macro-cells 1. A plurality of signal terminals 2 are provided on the parts of the circumference of each macro-cell 1 and power supply terminals, i.e., a Vcc terminal 3 and a GND terminal 4, are provided on the other parts of the circumference. A cell row 5 is electrically connected with an intra-macro-cell Vcc line 6 and an intra-macro-cell GND line 7 which are connected to the Vcc terminal 3 and the terminal 4 respectively. After a plurality of the macro-cells 1 are arranged on a chip 8, the layout of intra-chip Vcc lines 9 and intra-chip GND lines 10 is made for the Vcc terminals 3 and the GND terminals 4 of the respective macro-cells 1 and the intra-chip Vcc lines 9 and the intra-chip GND lines 10 are connected to a chip-circumferential Vcc line 11 and a chip-circumferential GND line 12 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array semiconductor device, and more particularly to a semiconductor device with an improved layout of power supply lines.

[Conventional technology]

In general, a gate array semiconductor device consists of elements such as transistors on a silicon wafer, and then interconnects the individual elements by forming wiring in an arbitrary wiring pattern to realize the required logical function. It looks like this. For this reason, in this type of gate array semiconductor device, the elements to be used are determined in advance based on the required logic circuit, the wiring that interconnects the determined elements is determined by automatic layout, and the wiring is performed. There is. in this case,
In a conventional gate array semiconductor device, the power supply lines (including ground lines) connected to each element are determined in advance, and only the signal lines connected to each element are automatically laid out.

[Problem to be solved by the invention]

In such conventional gate array semiconductor devices, the power supply line has a predetermined partial pattern layout, which is not necessarily the optimal layout for the layout of the logic circuit composed of each element, and may be inefficient. There is a problem. Further, since the power supply line is set in advance, the signal line must be arranged avoiding the power supply line, which imposes restrictions on the layout and reduces the degree of freedom in design.

The purpose of the present invention is to increase the efficiency of the power supply line, and
An object of the present invention is to provide a gate array semiconductor device that allows easy design of wiring layouts such as signal lines.

[Means to solve the problem]

The gate array semiconductor device of the present invention has a structure in which a functional circuit is divided into a plurality of macro cells, each macro cell is provided with a power terminal, and each power terminal is connected to a power line.

[Effect]

According to the present invention, the power supply line is connected using the power supply terminal provided in the macro cell, thereby increasing the efficiency of the power supply line and relaxing restrictions on the signal line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an example of a macro cell constituting a gate array semiconductor device of the present invention. This macro cell 1 is
It is one of several divisions of a logic circuit that performs the required functions using active elements such as transistors and diodes, and passive elements such as resistors. has been set up. Further, in other parts around the macrocell 1, there are power supply terminals independent of the signal terminal 2, that is, a VCC terminal 3 and a GND terminal 4.
are arranged respectively. The cell row 5 within the macrocell 1 is electrically connected as required by an intra-macrocell VCC line 6 and an intra-macrocell GND line 7 connected to the VCC terminal 3 and GND terminal 4, respectively.

FIG. 2 shows a layout of the macrocells 1 shown in FIG. 1 on a chip 8. After arranging a plurality of macrocells 1,
An intrachip VCC line 9 and a GND line 10 are laid out so as to supply a VCC potential and a GND potential, respectively, and are connected to a chip peripheral VCC line 11 and a chimp peripheral GND line 12, respectively. In addition, required signal lines (not shown) are laid out so that the signal terminals 2 of each macrocell 1 can perform their respective required functions.

As a result, in this chip 8, the signal line, the intra-chip VCC line 9, and the intra-chip GND line '1
0 can be designed at the same level. Therefore, it is possible to perform a design in which each line functions with maximum efficiency, and it is possible to increase the degree of freedom in design without imposing restrictions on the signal lines.

In this case, as shown in FIG. 3, two macrocells IA,
The 1000 knob 8A may be configured to connect a power line to each VCC terminal 3 and GND terminal 4 of the IB using the same 1000 knob internal VCC line 9 and the same intra-chip GND line 10.

With this configuration, the number of intra-chip VCC lines 9 and intra-chip GND lines 10 can be reduced.

[Effects of the Invention] As explained above, the present invention has a structure in which a power supply terminal is arranged in a macro cell and a power supply line connected to this power supply terminal is laid out together with a signal line connected to a signal terminal G. By designing the wiring pattern along with the signal line, it is possible to create a suitable layout for the power supply line and signal line for the macro cell, increasing its efficiency and easing design constraints on the signal line. This has the effect of improving the degree of freedom in design.

[Brief explanation of drawings]

FIG. 1 is a layout diagram showing the arrangement of internal wiring lines and terminals of a macrocell according to the present invention, FIG. 2 is a layout diagram of a chip of a gate array semiconductor device using the macrocell of FIG. 1, and FIG. FIG. 7 is a chip layout diagram showing a modification of the diagram. 1, IA, IB...macro cell, 2...signal terminal,
3...VCC terminal, 4...GND terminal, 5...cell row, 6...inside macro cell ■. , line, 7...GND line in the macro cell, 8...chip, 9...VCC line in the chip, 10...GND line in the chip, 11...VCC line around the chip, 12...chip Surrounding GND Lie Figure 3

Claims (1)

[Claims] 1. A gate array semiconductor characterized in that a functional circuit is divided into a plurality of macrocells, each macrocell is provided with a signal terminal and a power supply terminal, and a power supply line is connected to the power supply terminal of each macrocell. Device.