JPH043346Y2 - - Google Patents

Description

[Detailed explanation of the invention] <Technical field> This invention is a video processing system using a CRT controller.
Specify the address of the RAM, which will cause the video
Data corresponding to the specification is output from the RAM in parallel, the parallel data is converted to serial data by a data conversion circuit, and the serial data is displayed on a raster scan type CRT display device.
The present invention is applied to a computer system configured to display images on a CRT display screen, and particularly relates to a circuit for superimposing at least two display screens on a CRT screen.

<Prior Art> FIG. 8 is a schematic block diagram of a conventional personal computer system, in which reference numeral 1 is a CRT controller, 2 is a video RAM, and 3 is a shift register as a data conversion circuit. The CRT controller 1 gives an address signal specifying the address of the video RAM 2 to the video RAM 2, and the video RAM 2 stores data displayed on a CRT screen (not shown). is read out, and the shift register 3 converts the parallel data from the video RAM 2 into serial data and outputs it to a CRT display device (not shown). Here, the video RAM 2 stores data corresponding to the display position of the data on the CRT screen.

Therefore, if the number of characters displayed on the CRT screen is 25 rows x 40 columns = 1000 characters, the data storage capacity required for the video RAM 2 is equivalent to 1000 characters.
In the case of 25 rows x 80 columns = 2000 characters, 2000
A storage capacity corresponding to the number of characters is required.

By the way, there are cases where it is desired to display multiple display screens in a superimposed manner on a CRT screen. In such a case, if you use video RAM 2, which has a storage capacity of 2000 characters, this video RAM
2 can store data for two 1000-character screens, so it is possible to display two display screens superimposed on a CRT screen that has 1000 characters as one display screen. be. In this superimposition of display screens, conventionally, as shown in FIG. 9, the data of the first display screen is stored in the storage area 2a in the first half of the video RAM 2 from the first address to the intermediate address. The data for the second display screen is stored in the storage area 2b in the latter half from the middle address to the last address.

Therefore, when superimposing display screens,
The CRT controller 1, which specifies the addresses of each display screen, must alternately specify the addresses of the first half and the second half of the video RAM 2, making control of the designation extremely difficult.

<Purpose of the invention> The present invention was made in view of the above-mentioned circumstances, and it is possible to display a display screen superimposed on a CRT screen without requiring the CRT controller to specify complicated addresses. The purpose is to make it possible.

<Effects of the invention> In order to achieve this purpose, the invention has the following effects:
It is structured as follows.

In other words, the computer system of the present invention
The CRT display screen superimposition circuit has a storage capacity for at least the first and second display screens, and uses its even addresses as addresses for data constituting the first display screen, and uses its odd addresses as addresses for data constituting the first display screen. A video RAM configured as an address for data constituting the second display screen, a latch circuit that latches data from the video RAM in response to a character clock, and a parallel input from the video RAM provided through the latch circuit. Data conversion having a first data conversion circuit corresponding to the first display screen that converts and outputs data into serial data, and a second data conversion circuit corresponding to the second display screen that converts and outputs parallel data from the video RAM into serial data. a selector that selectively outputs the outputs of both data conversion circuits in dot units based on a selection control signal from a selector controller; and a selector that selectively outputs the outputs of both data conversion circuits in dot units based on a selection control signal from a selector controller; a selector controller that forms and outputs the selection control signal based on a display screen number switching signal that specifies the number of display screens and a display priority signal that specifies which of the first display screen or the second display screen should be prioritized; It is configured.

<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings. FIG. 1 is an overall schematic block diagram of this embodiment. In FIG. 1, reference numeral 10
20 is a CRT controller which supplies an address signal specifying the address of the video RAM 20 to the video RAM 20, and 20 stores data to be displayed on a CRT screen (not shown), and the stored data is read out by the address signal from the CRT controller 10. A shift register 30 serves as a data conversion circuit that converts parallel data from the video RAM 20 into serial data and outputs the serial data to a CRT display device (not shown). Here, in the video RAM 20,
The data is stored corresponding to the display position of the data on the CRT screen.

The video RAM 20 has a storage capacity equivalent to two or more CRT screens, and corresponds to at least the first and second display screens to be superimposed, and stores the even-numbered addresses as data constituting the first display screen. , and the odd numbered address is configured as the address of the data constituting the second display screen. The shift register 30 has first and second display screens corresponding to the first and second display screens, respectively.
It is composed of shift registers 30a and 30b.

Reference numeral 40 indicates both the shift registers 30a, 3.
A latch circuit 40 is provided between one of the shift registers 30a and the video RAM 20 and latches the output of the video RAM 20, and 50 is a selector that selectively outputs the outputs of both the shift registers 30a and 30b. 60 is a selector controller that controls the operation of the selector 50.

The block diagram in FIG. 2 shows a specific example of the selector controller 60, which includes a pair of front-stage AND gates 70, which introduce the outputs of the first shift register 30a and the second shift register 30b, respectively.
71, and each pre-stage AND gate 70, 71 includes:
The display priority signal from the CPU (also serves as the display screen switching signal) or that signal is sent to the front stage inverter 8.
A signal inverted at 0 is input. Both front rows
The outputs of AND gates 70 and 71 are input to OR gate 90. The output of this OR gate 90 is introduced into one 100 of a pair of rear-stage AND gates 100 and 101. This latter stage AND gate 100 has a CPU
A display screen number switching signal from . Further, the display screen number switching signal is inverted by a second-stage inverter 110 and inputted to the other second-stage AND gate 101. The outputs of these two latter-stage AND gates are input to a NOR gate 120. This NOR gate 120
The output is input to the select 50 as a selection control signal.

The video RAM 20 stores data constituting a plurality of screens (two screens in this embodiment) as shown in the block diagram of FIG. The data of the two display screens are respectively stored at odd addresses.

Next, in a computer system having a superposition circuit having the above configuration, as shown in the explanatory diagram of FIG. is possible. Below are videos in each display mode.
RAM access timing will be explained based on the time chart shown in FIG.

(b) Single screen display in 80-column mode A video is displayed every cycle of the character clock.
One address of RAM20 is specified sequentially, and the video
The RAM 20 sequentially outputs data at each address. Both first and second shift registers 30a, 30
b latches the same parallel data, serializes it, and outputs it. The selector controller 60 selects one of the data input from both shift registers 30a, 30b, but since the data from both shift registers 30a, 30b are the same, it may select either data. As a result, the data sequentially read out from the video RAM 20 is displayed on the CRT screen in the order in which they were read out, forming a display screen as shown in FIG.

(b) Single screen display in 40-column mode The character clock cycle is twice as long as the cycle in 80-column mode, but the video RAM is displayed twice for each cycle of this character clock.
20 are accessed. Therefore video RAM
The access cycle of 20 is the same length as in the 80 column mode. Latch circuit 40 latches data from video RAM 20 on the down edge of the character clock. The timing of this latch is shown in the video.
The timing is right for the RAM 20 to output data at even addresses (hereinafter referred to as even data), and the latch circuit 40 latches the even data. Therefore, even data is transferred to the first shift register 30a with a delay of half a cycle of the character clock.
Enter. At this time, the second shift register 3
Data at odd addresses (hereinafter referred to as odd data) is input to 0b. Therefore, when even data is output from the first shift register 30a, the next odd data is output from the second shift register 30b. The selector 50 selects either odd or even data in response to a control signal from the selector controller 60. If even number data is selected, the first display screen consisting of even number data is displayed independently on the CRT screen as shown in FIG. 7A.
If odd number data is selected, a second display screen consisting of odd number data is independently displayed on the CRT screen as shown in FIG. 7B.

Switching between the first display screen and the second display screen can be done instantly, so it is possible to display simple animations by rewriting the contents of one display screen while the other display screen is being displayed. .

(c) Two-screen superimposed display The series of operations from accessing the video RAM 20 to outputting both the first and second shift registers 30a and 30b is the same as in the case of the single-screen display in the 40-column mode (b) above. Even data is output from the first shift register 30a, and the next odd data is output from the second shift register 30b at the same timing. The selector 50 alternately selects even data and odd data. By this,
The first display screen and the second display screen will be displayed in a superimposed manner on the CRT screen. In this case, either the first display screen or the second display screen is displayed with priority according to the display priority signal input from the CPU to the selector controller 60. In this way, when overlapping screens, the display priority can be set.

<Effects of the invention> As described above, according to the invention, on the CRT screen,
One screen can be displayed individually or multiple screens can be displayed in a superimposed manner.Moreover, in the single screen display, the display screen can be switched, and in the superimposed display, complex addresses can be displayed on the CRT controller. There is no need to request specification.

Furthermore, since the screens are superimposed on a dot-by-dot basis, it is possible to express minute overlapping conditions, and from this point of view as well, the expression on the screen becomes even wider.

[Brief explanation of the drawing]

Figures 1 to 7 show an embodiment of the present invention, in which Figure 1 is a schematic block diagram of the entire circuit, Figure 2 is a block diagram of the selector controller, and Figure 3 is a block diagram of the selector controller.
The figure is a configuration diagram of the video RAM, Figure 4 is an explanatory diagram showing the display state, Figure 5 is a time chart, and Figure 6 is
Configuration diagram of display screen in 80-column mode, Figure 7 A, B
are respectively configuration diagrams of display screens in 40-column mode. FIG. 8 is a block diagram of the main parts of a conventional computer system, and FIG. 9 is a configuration diagram of its video RAM. 10...CRT controller, 20...video
RAM, 30a...first shift register, 30b
...Second shift register, 40...Latch circuit,
50...Selector, 60...Selector controller.

Claims (1)

[Claims for Utility Model Registration] CRT controller 10, video RAM 20, data conversion circuit 30, latch circuit 40, selector 5
0 and a selector controller 60, the CRT controller 10 specifies the address of the video RAM 20, and the video RAM 20 controls at least the first and second display screens of the CRT screen of the raster scan type CRT display device. , and its even address is the address of the data constituting the first display screen, and its odd number address is the address of the data constituting the second display screen.
The latch circuit 40 is configured as an address for data composing the display screen, and outputs data in parallel in response to address designation from the CRT controller 10. The latch circuit 40 outputs data from the video RAM 20 in response to the character clock. The data conversion circuit 30 has a first data conversion circuit 30a corresponding to the first display screen and a second data conversion circuit 30b corresponding to the second display screen. The data conversion circuit 30a converts and outputs the parallel data from the video RAM 20 provided via the latch circuit 40 into serial data, and the second data conversion circuit 30b converts and outputs the parallel data from the video RAM 20 into serial data. , the selector 50 selectively outputs the outputs of both data conversion circuits 30a and 30b in units of dots based on a selection control signal from a selector controller 60; , 30b, a display screen number switching signal that specifies single screen display or two screen overlapping display, and a display priority signal that specifies whether to give priority to the first display screen or the second display screen. A CRT for a computer system, wherein the CRT forms and outputs the selection control signal.
Display screen superimposition circuit.