JPH04338859A - Computer device - Google Patents

Abstract

PURPOSE:To perform the peripheral operation without waiting for the processing of a CPU at the time of accessing a memory by a peripheral device by providing the CPU, memories, and the peripheral device and connecting data busses from memories independently of each other. CONSTITUTION:An instruction bus 46 and a first data bus 44 connected to an instruction memory 47 are connected to a CPU 41, and the bus 44 and a second data bus 45 are connected to a data memory 42, and the bus 45 is connected to a peripheral circuit 43. Data is transferred between the peripheral circuit 43 and the data memory 42 through the bus 45 in the period when the CPU 41 does not access the data memory 42 in the instruction cycle of the CPU 41. Preferably, this period is the period privately provided in the instruction cycle or the period of an instruction which does not access the data memory 42.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a central processing unit (hereinafter referred to as CP).
The present invention relates to a computer device having a memory (denoted as U), a memory, and other peripheral devices, and particularly relates to a computer device in which data and memory of a CPU can be independently accessed from a peripheral device during execution of an instruction by a central processing unit.

0002

[Prior Art] In a conventional computer device that integrates a CPU, memory, and peripheral devices, one data
bus to CPU 21, data memory 22, peripheral devices 23
Share with. The data bus 24 is used when the CPU 21 accesses the data memory 22, when the CPU 21 accesses the peripheral device 23, and when the peripheral device 23 accesses the data memory 22. CPU21
accesses the data memory 22 and the CPU 21
When accessing the peripheral device 23, it corresponds to an instruction from the CPU 21. However, the peripheral device 23
2 may be accessed in response to instructions from the CPU 21, or the peripheral device 23 may require the data in the data memory 22 independently for its operation, regardless of the instructions from the CPU. The latter is called a direct memory access operation (hereinafter referred to as a DMA operation).

DMA operation When it is necessary to transfer a larger amount of data from the data memory 22 to the peripheral device 23 in a short time than the amount of data transferred from the data memory 22 to the peripheral device 23 by one command of the CPU 21, used.

[0004] Normally, the CPU 21 is
In the case of a PU, the amount of data that can be transferred from the data memory 22 to the peripheral device 23 with one instruction is about 8 bits. For example, when the peripheral device 23 executes 3 instructions during one instruction execution time of the CPU 21,
If 2 bits are required, the data/memory of the CPU21
This is because if the peripheral device 23 directly accesses the data memory 22 without any access operation, the peripheral device 23 only needs to access it four times during one instruction of the CPU 21 at its own timing.

When performing a DMA operation, the operation of the CPU 21 is stopped so that the data controlled by the CPU 21 and the data controlled by the peripheral device 23 do not interfere with each other on the data bus 24, and the data bus 24 is connected to the peripheral device. Released on the 23rd.

The peripheral device 23 issues a DMA operation request 25 to the CPU 21, and the CPU 21 puts the DMA operation into a state where it can be executed, releases the data bus 24, and issues a DMA permission signal 26.
is sent to the peripheral device 23, and the operation is stopped until a DMA operation cancellation signal 27 is issued from the peripheral device 23.

[0007]

[Problems to be Solved by the Invention] Since the DMA operation uses the data bus 24 in FIG. 2 for data transfer to the peripheral device 23, the CPU operation must be stopped during that time, which reduces the apparent CPU processing speed. decreases. Figure 3 shows the situation.

A in FIG. 3 shows the CPU when there is no DMA operation.
This is the operation timing. B in Figure 3 shows that the DMA operation is CP.
This is a case where every other instruction of U is executed. For example, CPU
If the instruction execution time is 2μ seconds and the time required for DMA operation is also 2μ seconds, then in Figure 3A, the CPU instruction execution time is 2μ seconds, but in Figure 3B, the CPU instruction execution time is apparently 4μ seconds. It becomes seconds.

Furthermore, in the above example, the DMA operation time CPU
The execution time for one instruction is the same as that of 1, but it may take even longer depending on the processing content of the peripheral device. In other words, since the data bus used for data processing by the CPU and the data bus used by peripheral devices are the same, if data several times the bit width of the data bus is transferred to the peripheral device, the DMA operation This is because the period increases.

Furthermore, if the processing content of the peripheral device is asynchronous with the CPU operation, even if a DMA operation request is issued from the peripheral device, depending on the CPU operation status, the CPU
A DMA operation permission signal is not sent from the peripheral device, and the operation of the peripheral device stops during that time.

[0011] When DMA operations are used, there are cases in which both the processing speed of the CPU and the processing speed of peripheral devices become slow.

[0012] The faster the execution processing speed that a device external to the computer system requires of the computer system, the more disadvantageous it becomes. Furthermore, in order to increase the execution processing speed with such a configuration, it is necessary to increase the processing speed of the CPU itself. If the CPU is an integrated circuit, the size of the internal transistors must be increased, leading to an enlargement of the integrated circuit and further resulting in large power consumption.

[0013]

A computer device of the present invention has a central processing unit, an instruction memory, a data memory, and a peripheral circuit, and the central processing unit has an instruction bus connected to the instruction memory, and a first A data bus is connected, and the data memory is connected to a first data bus and a second data bus.
a second data bus is connected to the peripheral circuit, and data transfer between the peripheral circuit and the data memory transfers the data memory to the central processing unit during an instruction cycle of the central processing unit. It is characterized in that it is performed via the second data bus during periods when the data bus is not being accessed.

[0014] The period during which the central processing unit does not access the data memory during the instruction cycle of the central processing unit is a period provided exclusively during the instruction cycle, or a period during which the data memory is not accessed. This is the period of instruction.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. CPU1
receives instructions from instruction memory 7 via instruction bus 8 and accesses data memory 2 or peripheral device 3 via data bus 4 in accordance with the instruction. Data transfer between peripheral device 3 and data memory 2 takes place via a dedicated data bus 5. FIG. 5 shows the operating status of the CPU 1 during one instruction. One instruction of the CPU 1 is divided into four timings, and the data memory 2 can only be accessed once at each timing. During timing 51, CPU1 receives data.
Memory 2 is not accessed, timings 52, 53, 54
Then, CPU 1 accesses data memory 2.

For example, if the data bus 4 is 8 bits,
The dedicated data bus 5 is 32 bits, and the CPU 1 is
The instruction cycle is assumed to be 2 μsec. Now, while the CPU 1 is operating, the peripheral device 3 is operating asynchronously with the CPU 1. It is assumed that the peripheral device 3 requires 32 bits of data every 2 μsec due to its operation. Peripheral device 3 accesses data memory 2 via dedicated data bus 5 during timing 52 during the CPU 1 instruction cycle. Dedicated data/
Unlike data bus 4, bus 5 has a bit width of 32 bits.
s, 32 bits from data memory 2 at one time
Since the timing 51 is always reserved for data transfer between the peripheral device and the data memory 2 while the CPU 1 is operating, the peripheral device 3 does not need to take the trouble to request permission from the CPU 1. do not have.

FIG. 4 shows a second embodiment of the present invention. Example 1
The difference is that the data memory 2 can be accessed independently by the CPU 41 and the seed device 43.

[0019]

Effects of the Invention When a peripheral device accesses a memory, the peripheral device can operate without waiting for CPU processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

FIG. 3 is a timing chart of a conventional circuit.

FIG. 4 is a diagram of a second embodiment of the present invention.

FIG. 5 is a timing chart of the present invention.

FIG. 6 is an embodiment diagram of the present invention.

Claims (4)

[Claims] [Claim 1] A central processing unit, an instruction memory, and a data
In a computer device having memory and peripheral circuits,
An instruction bus connected to the instruction memory and a first data bus are connected to the central processing unit; the data memory is connected to the first data bus and a second data bus; A data bus is connected to the peripheral circuit, and data transfer between the peripheral circuit and the data memory is performed during a period when the data memory is not being accessed by the central processing unit during an instruction cycle of the central processing unit. A computer device characterized in that it operates via a second data bus. 2. A claim characterized in that a period in which the central processing unit does not access the data memory during an instruction cycle of the central processing unit is a period exclusively provided during the instruction cycle. The computer device according to item 1. 3. A period during an instruction cycle of the central processing unit in which the data memory is not accessed by the central processing unit is a period of an instruction in which the data memory is not accessed. Computer equipment as described. 4. An area that is not accessed by the central processing unit during a period when the central processing unit is accessing the data memory can be accessed by the peripheral device. Computer equipment as described.