JPH0434027U - - Google Patents

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Publication number
JPH0434027U
JPH0434027U JP7518590U JP7518590U JPH0434027U JP H0434027 U JPH0434027 U JP H0434027U JP 7518590 U JP7518590 U JP 7518590U JP 7518590 U JP7518590 U JP 7518590U JP H0434027 U JPH0434027 U JP H0434027U
Authority
JP
Japan
Prior art keywords
circuit
phase
locked loop
loop filter
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7518590U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7518590U priority Critical patent/JPH0434027U/ja
Publication of JPH0434027U publication Critical patent/JPH0434027U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係るロツクアツプタイム短
縮のフエーズロツクドループ回路の実施例を示す
フエーズロツクドループ回路を構成するループフ
イルタ回路図である。第2図及び第3図は従来例
を示し、第2図はフエーズロツクドループ周波数
シンセサイザを示す構成ブロツク図、第3図はル
ープフイルタの回路図である。 主な符号の説明、2……電圧制御発振回路、6
……位相比較器、7……周波数制御信号入力端子
、Q,Q……トランジスタ、R〜R……
抵抗、C,C……コンデンサ。
FIG. 1 is a loop filter circuit diagram constituting a phase-locked loop circuit showing an embodiment of the phase-locked loop circuit for shortening lock-up time according to the present invention. 2 and 3 show a conventional example. FIG. 2 is a block diagram showing a phase-locked loop frequency synthesizer, and FIG. 3 is a circuit diagram of a loop filter. Explanation of main symbols, 2... Voltage controlled oscillation circuit, 6
... Phase comparator, 7 ... Frequency control signal input terminal, Q 1 , Q 2 ... Transistor, R 1 to R 6 ...
Resistor, C 1 , C 2 ... capacitor.

Claims (1)

【実用新案登録請求の範囲】 基準周波数発振器と、位相比較器と、電圧制御
発振器と、ループフイルタとで構成されるフエー
ズロツクドループPLL回路において、 前記フエーズロツクドループ回路の構成要素で
ある抵抗及びコンデンサと、トランジスタとから
なるループフイルタに微分回路と、トランジスタ
によるスイツチング回路とを設け、スイツチング
回路のON/OFFによつてループフイルタの時
定数を変えロツクアツプタイムを短縮するように
構成したことを特徴とするロツクアツプタイム短
縮のフエーズロツクドループ回路。
[Claims for Utility Model Registration] In a phase-locked loop PLL circuit comprising a reference frequency oscillator, a phase comparator, a voltage-controlled oscillator, and a loop filter, a resistor that is a component of the phase-locked loop circuit A differential circuit and a switching circuit using a transistor are provided in a loop filter consisting of a capacitor and a transistor, and the time constant of the loop filter is changed by turning ON/OFF the switching circuit to shorten the lock-up time. A phase-locked loop circuit that shortens lock-up time.
JP7518590U 1990-07-17 1990-07-17 Pending JPH0434027U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7518590U JPH0434027U (en) 1990-07-17 1990-07-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7518590U JPH0434027U (en) 1990-07-17 1990-07-17

Publications (1)

Publication Number Publication Date
JPH0434027U true JPH0434027U (en) 1992-03-19

Family

ID=31615541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7518590U Pending JPH0434027U (en) 1990-07-17 1990-07-17

Country Status (1)

Country Link
JP (1) JPH0434027U (en)

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