JPH0434170B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for monitoring whether or not a frequency abnormality has occurred in a common clock pulse used by each processor in a control device equipped with a plurality of processors. It is something.

[Conventional technology]

In railway signal safety control equipment, etc., high reliability and fail-safe performance are required, and equipment equipped with multiple processors is generally employed.One example of this is shown in the block diagram of Figure 4. It's summery.

That is, processors (hereinafter referred to as CPUs) 1 ₁ and 1 ₂ of the same type using microprocessors or the like are provided, and fixed memories (hereinafter referred to as ROMs) 2 1 and 2 2 of the same type and variable memories (hereinafter referred to as ROM) 2 ₁ and 2 ₂ of the same type are provided for each processor. below,
RAM) 3 ₁ , 3 ₂ and input/output circuit (hereinafter referred to as I/
O) 4 ₁ and 4 ₂ are arranged around the periphery, and each set is connected by bus bars 5 ₁ and 5 ₂ , and the CPUs _{1 1} and 1 ₂ are connected to a common oscillator (hereinafter referred to as OSC) 6. A clock pulse CLK _C is supplied, and based on this, the CPUs _{1 1} and 1 ₂ perform control operations in synchronization with each other.

Here, CPU1 ₁ , 1 ₂ is ROM2 ₁ , 2
Execute the same instructions stored in ₂ individually,
Control operations including various arithmetic operations are performed in parallel with each other while accessing necessary data from RAM3 ₁ and ₃₂ , and control decisions are made according to input data via I/Os ₄₁ and ₄₂ . Taue, I/
Control data is sent via O4 ₁ and O4 ₂ , and the control operation includes time processing such as frequency determination of input data and timer operation according to input data.

Therefore, temporal processing is executed based on the clock pulse CLK _C from OSC 6, and if this frequency changes or oscillation becomes unstable, the temporal processing results will be incorrect and the control situation may become dangerous. To prevent this, an OSC 7 that generates a clock pulse CLK _S for monitoring is separately provided, and this generates a clock pulse CLK _S with the same frequency as the clock pulse CLK _C , which is sent to the CPU 1.
Counters corresponding to each of ₁ , 1 _{and 2} (hereinafter referred to as CUT)
8 ₁ and 8 ₂ respectively, thereby causing each clock pulse CLK _S to be counted.

On the other hand, CPUs 1 ₁ and 1 ₂ use the clock pulse CLK _C
The timing of a certain period is defined by timer processing based on , _and the count values of CUT8 ₁ and _{8 2} are checked accordingly.
The CUTs ₈₁ and ₈₂ repeat counting the clock pulse CLK _S at regular intervals, so that if the frequencies of the clock pulses CLK _C and CLK S are the same, the clock pulses CLK C and CLK _S are kept constant. While each count value between cycles is always constant, if an abnormality occurs in the generation status of clock pulse CLK _C , the constant cycle will fluctuate, and accordingly, each count value at the time of check will be outside the constant range. This is used to determine whether the clock pulse CLK _C is abnormal.

In addition, each data bit of bus lines 5 ₁ and 5 ₂ including each count value of CUT 8 ₁ and 8 ₂ is connected to a comparator (hereinafter referred to as
CMP) 9, and when both inputs match, an alternating signal is sent out and this is sent to the I/O4.
The output data of I/Os 4 ₁ and 4 ₂ supplied to I/Os 4 ₁ and _{4 2} is in the form of an alternating signal.
The output data of CPU 1 1 and 1 ₂ is also at a constant level, and in the circuit that receives the output data, the alternating signal is rectified and used as a control output, so if there is a mismatch between the control operations of CPU _{1 1} and 1 ₂ , the control output disappears, and the relay etc. will definitely recover and the control situation will be on the safe side.

[Problem that the invention seeks to solve]

However, in the configuration shown in FIG. 4, CUT8 ₁ ,
8 ₂ is required, the configuration becomes complicated, and
If even a one-count difference occurs between the count values of _CUT81 and _CUT82 , the alternating signal of CMP9 will be at a constant level even in cases where there is no practical problem, causing the problem that the control operation will be stopped more than necessary. It is occurring.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in the above-mentioned control device, a monitoring clock pulse having the same frequency as the common clock pulse is separately generated, and this monitoring clock pulse is counted by a presettable counter, and the monitoring clock pulse is counted by a presettable counter, and the above-mentioned clock pulse is generated at regular intervals based on the common clock pulse. Different initial values are alternately preset to the counter, and the count value of the counter immediately before presetting is compared with the value obtained by adding the count number generated by the monitoring clock pulse during a certain period to the initial value. Therefore, it was determined that an abnormality occurred in the common clock pulse.

[Effect]

Therefore, the count value at each fixed period is alternately different, and it is possible to monitor abnormalities in the presettable counter and the monitoring clock pulse.If these and the common clock pulse are normal, the count value at each fixed period can always be predicted. However, if an abnormality occurs in the common clock pulse, the count value and the predicted value will not match.

〔Example〕

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

Figure 1 is a block diagram showing the configuration, which is almost the same as Figure 4, but with a common clock pulse.
Monitoring clock pulse with the same frequency as CLK _C
The output of the OSC 7, which separately generates CLK _{S ,} is given to a presettable counter (hereinafter referred to as PCT) ₁₁ , which counts the clock pulse CLK _S. Bidirectional and unidirectional buffer circuits (hereinafter referred to as BAF) 12 and 13 are respectively inserted between them.

FIG. 2 is a timing chart showing the operating status and waveforms of each part in _{FIG .} By processing, PCT11
, a different initial value A or B is preset at regular intervals T via the BAF 12, and the CPUs _{1 1} and 1 ₂ alternately read the count value of the PCT 11 immediately before this preset via the BAF 12 and 13, and calculate the count value. It is designed to check the following.

Therefore, the initial values A and B are alternately preset to the PCT 11 at each timing a, and the PCT 11 counts the clock pulses CLK _S b for a fixed period T based on these values, and this is repeated. If the count number is n, the count contents of PCT11 are as shown in c.
Immediately before the end of the constant period T for which the initial value A is preset, the count value becomes A+n, and just before the end of the constant period T for which the initial value B is preset, the count value becomes B+n, and then the count value changes to A according to the preset value.
Using +n or B+n as a predicted value, this predicted value and the count value are compared, and if they match, it is determined that the clock pulse CLK C is abnormal, or if they do not match, it is determined that the clock pulse CLK _C is abnormal or the OSC7 to PCT11 are abnormal.

Note that if the initial value is only A or B, then A+
When the count value reaches n or B+n
When the PCT 11 stops counting, the count value always matches the predicted value even though there is an abnormality in the OSC 7 to PCT 11, and these abnormalities cannot be determined.

FIG. 3 is a flowchart of the interrupt processing performed by the CPU ₁₁ , which is executed in accordance with timing a in _FIG . Check "Even number flag set?" 102,
If this is Y (YES), it is a preset constant period of initial value A, so "N _C = A + n?" 1
11 is judged, and if this is Y, it is normal,
After performing "even flag reset" 112, "B preset to PCT" 113 is performed, and the process returns to the main routine.

On the other hand, when step 102 is N (NO),
It is a preset constant period of initial value B,
Determine “N _C = B + n?” 121, and if it is Y, it is normal, so “Even number flag set” 123
After performing "A preset to PCT" 124, the program returns to the main routine.

Regarding the above, if the comparison result at step 111 or 121 is non-coincidence, and either one is N, the process moves to "abnormality processing" 131, where control is stopped, an alarm is displayed, etc.

It should be noted that the CPU ₁₂ does not need to perform presetting, but due to the relationship with the CMP 9, the same processing may be performed.

Therefore, the purpose can be sufficiently achieved with a single PCT 11, and since a plurality of counters are not used, there is no need to stop the control more than necessary, and the control situation becomes stable.

However, it can also be applied to the case where the configuration of the CPU _{1 1} , 1 ₂ to the I/O _{4 1} , 4 ₂ is a multiprocessor system with three or more sets, and the timing of the constant period T is performed by a separate timer, and this is controlled by the clock pulse. Various modifications are possible, such as being able to operate using CLK _C or setting a permissible range for comparison of count values.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a common clock pulse can be reliably monitored with a simple and inexpensive configuration, and a plurality of CPUs operated by a common clock pulse can be provided without causing control stoppage. , remarkable effects can be obtained in various control devices that perform temporal processing.

[Brief explanation of drawings]

1 to 3 show an embodiment of the present invention, FIG. 1 is a block diagram, FIG. 2 is a timing chart showing the operating status of each part in FIG. 1, and FIG. 3 is a flowchart of interrupt processing. , FIG. 4 is a block diagram of a conventional example. 1 ₁ , 1 ₂ ... CPU (processor), 2 ₁ , 2 ₂ ...
ROM (fixed memory), 3 ₁ , 3 ₂ ... RAM (variable memory), 6, 7 ... OSC (oscillator), 11 ... PCT
(presettable counter), CLK _C , CLK _S ...
Clock pulse, T... constant period, A, B... initial value.

Claims (1)

[Claims] 1. In a control device that includes a plurality of processors and in which each of the processors performs the same temporal processing in synchronization with each other using a common clock pulse, a monitoring clock pulse having the same frequency as the clock pulse is separately generated, and the monitoring clock pulse is While counting by a presettable counter, different initial values are preset to the counter alternately at fixed cycle timing based on the common clock pulse, and the count value of the counter immediately before the preset and the constant value are set to the initial value. A clock pulse monitoring method for a control device, characterized in that a value obtained by adding up the counts of monitoring clock pulses during a cycle is compared with a value obtained by adding up the number of counts caused by a monitoring clock pulse during a cycle, and it is determined that an abnormality has occurred in the common clock pulse due to a discrepancy in the comparison result.