JPH04344573A - Wiring processing method in cad system - Google Patents

Abstract

PURPOSE:To reduce the maximum delay time of a net by locating a branch point close to a load pin as far as possible. CONSTITUTION:A control means 101 reads locational information of blocks, terminal positional information for each block, and so on from a storage means 104 to obtain a position of the source pin and positions of a plurality of load pins. A cost estimating means 102 estimates a cost of each point on a wiring pattern connecting between a load pin first selected from a plurality of load pins and the source pin, sets a point with the minimum cost as the branch point to a load pin secondly selected from the wiring pattern, and the same is applied to other load pins to successively obtain branch points on the wiring pattern. A wiring means 103 prepares a wiring pattern between the source pin and the first selected load pin, and wiring patterns that are branched to each load pin from that wiring pattern.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring processing method in a CAD system, and more particularly to a wiring processing method in a CAD system for designing wiring for LSIs, printed circuit boards, etc.

0002

[Background Art] Conventionally, in wiring design for LSIs, printed circuit boards, etc., two wires are connected without being aware of the distinction between source pins and load pins of a net, taking into account wiring prohibited areas.
Wiring was done so that the distance between pins between points was the shortest.

[0003] References include VLSI DESIGN, 4
Monthly issue, 1984, pages 35-43.

0004

[Problem to be solved by the invention] The above-mentioned conventional CAD
The wiring processing method in the system is that when wiring a net with a fanout of 2 or more, considering the reflection of electrical signals at the load pin, the maximum delay time from the source pin is
Since it is proportional to the sum of the wiring length from the source pin to the farthest load pin and the wiring length from the load pin branched from the wiring to the branch point, the load pin The maximum delay time will be smaller if the branch is closer to . However, the conventional method described above has the disadvantage that branching may occur near the source pin, and in that case, the maximum delay time becomes longer than when branching near the load pin.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring processing method in a CAD system that can place branch points as close to load pins as possible and reduce the maximum net delay time.

[0006]

[Means for Solving the Problems] A wiring processing method in a CAD system of the present invention is a wiring processing method in a CAD system when wiring nets with a fanout exceeding 1 in wiring design including LSI and printed circuit boards. (A) storage means for storing logical information, block arrangement information, and terminal position information for each block;
B) Regarding the wiring pattern connecting the source pin and the first load pin of the target net, consider the fact that the electrical signal from the source pin is reflected by the first load pin, and calculate the cost of each point on the pattern. to generate first costing data, then costing from the second load pin to each point on the wiring pattern to generate second costing data, and then calculating the first costing data. For the remaining load pins, the point with the minimum total cost is set as the branching point from the wiring pattern to the second load pin. (C) costing means for sequentially finding branching points from the wiring pattern to the remaining other load pins, (C) wiring the wiring pattern between the source pin and the first load pin, and then the costing means; wiring means for wiring a wiring pattern to be branched from the wiring pattern to each load pin based on the branch point information for each load pin obtained by The positions of the source pin and the number of load pins exceeding 1 of the target net are determined from the terminal position information of It is configured to route a wiring pattern between the source pin and the first load pin, and a wiring pattern branching from the wiring pattern to each of the remaining load pins.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a wiring processing method in a CAD system according to the present invention.

The wiring processing method in the CAD system of the present embodiment shown in FIG.
04. Regarding the wiring pattern connecting the source pin of the target net and a load pin selected from among multiple load pins, consider that the electrical signal from the source pin is reflected by the load pin, and consider the pattern as a collection of points. Cost each point on the pattern to generate costing data, then cost from the selected load pin to each point on the wiring pattern to generate costing data, and calculate the previously determined cost. Add the costing data and the costing data obtained by calculating the cost from the second selected load pin to each point on the wiring pattern, and calculate the point with the minimum total cost from the second selected load pin from the wiring pattern. For other load pins, the costing means 102 sequentially determines the branch points to the load pin selected from the wiring pattern. wiring means 103 for wiring a wiring pattern between the wiring pattern and the pin, and then wiring a wiring pattern to be branched from the wiring pattern to each load pin based on the branch point information for each remaining load pin obtained by the costing means 102; The logical information, block arrangement information, and terminal position information for each block are read out from the storage means 104, and the positions of the source pin and a plurality of load pins of the target net are respectively determined, and from among the load pins, the first one located farthest from the source pin is selected. The control means 101 selects a load pin and controls the above means.

[0010] In the above explanation, "cost" refers to the distance between the source pin, load pin, wiring pattern, and branch point, and the weighting of each point on the wiring pattern using the obtained values. The weighting values obtained are shown below.

Next, the operation will be explained.

FIG. 2 is a diagram showing a state in which a forward search using the maze method is performed using an unconnected load pin as a starting point and targeting a wiring pattern.

The operation of the wiring processing method in the CAD system of this embodiment shown in FIG. 1 targets nets with a fanout of 2 or more, but here, as shown in FIG.
The case where there is one source pin and two load pins will be explained.

In FIG. 1, control means 101 retrieves the logic information of the target net from storage means 104 and determines the source pin and load pin. Next, the block arrangement information and the pin position information for each block are extracted, and the pin positions of the target net are determined. Once the pin positions are determined, the two load pins 202 and 203 in FIG.
Select the load pin that is farthest from the source pin. That is, here, the case where the load pin 202 is selected from the two load pins will be explained as an example.

Next, the control means 101 controls the wiring means 103
Start. The activated wiring means 103 wires a wiring pattern 207 between the selected load pin 202 and source pin 201. Then, the control means 101 activates the cost adding means 102. The activated costing means 102 adds costs to the wiring pattern 207 connecting the source pin 201 and the load pin 202.

[0016] When considering the delay time of the electrical signal when calculating the cost, taking into account that the electrical signal is reflected at the load pin 202, the delay time from the source pin 201 to the load pin 202 is It is necessary to consider the delay time including the delay time to the branch point. Now, assuming that the delay time per unit length is constant, the delay time is proportional to the wiring length, so the wiring pattern 207 is treated as a set of points, and the source pin 2
A value obtained by adding the wiring length from the load pin 202 to the branch point to the wiring length from the load pin 202 to the wiring length from the load pin 202 can be calculated as the distance to that point, and this value can be used to calculate the cost. The cost of each point on the wiring pattern obtained in this manner is shown in FIG. In FIG. 3, the cost on the pattern at the position of the load pin 202 is:
The cost on the pattern at the position of the source pin 201 is "36", but the cost on the pattern at the position of the source pin 201 is from the source pin 201 to the load pin 202. The cost (“18”) corresponding to the distance and the cost (“18”) corresponding to the distance from the load pin 202 to the branch point (in this case, the source pin 201 itself) are added. Note that the wiring prohibited area in FIG. 3 is an area through which wiring cannot pass.

[0017] Also, the cost from the load pin 203 is
Although it is shown in FIG. 3 as a cost from the load pin 203. This can be found as follows. That is, the costing means 102 performs a forward search using the maze method, which is one of the wiring algorithms, using the load pin 203 as a starting point, and as shown in FIG. (indicated by numbers up to 16). This is repeated until all points of the wiring pattern 207 connecting the source pin 201 and the load pin 202 are reached. Next, the label value on the wiring pattern 207 is taken as the cost from the load pin 203, and this value is added to the previously determined cost of each point on the pattern, and this value is taken as the total cost of each point on the wiring pattern 207. As a result, the total cost for each point of the wiring pattern 207 is as shown in FIG.

Next, the wiring means 103 connects the wiring pattern 2
07 and the load pin 203 are connected. Wiring pattern 2
07, the point where the total cost is the minimum is defined as the branching point of the net. Looking at FIG. 3, any point between the branch point 210 and the load pin 202 has a minimum cost of "33", and any point can be selected, but here, the cost from the load pin 203 is "33". Select the branch point 210 that is the smallest at 10''. And branch point 210
Using the wiring pattern 2 as a starting point, a maze method backward search is performed to the load pin 203 while avoiding the wiring prohibited area, and wiring pattern 2 shown in FIG.
08 can be obtained.

In the conventional method, the branch point is determined based only on the cost from the load pin 203 without considering the cost from the load pin 202. Therefore, from FIG. 3, the branch point 210 or 211 is selected as the branch point where the cost from the load pin 203 is "10" and is the minimum. Therefore, the connection pattern between the wiring pattern 207 and the load pin 203 becomes the wiring pattern 208 or the wiring pattern 209. Here, there is no problem if the wiring pattern 208 is selected, but if the wiring pattern 208 is selected, the maximum delay time increases. On the other hand, when the method of the present invention is used, the wiring pattern 208 is always selected and the minimum delay time can be obtained.

[0020]

[Effects of the Invention] As explained above, the wiring processing method in the CAD system of the present invention is such that in order to perform wiring while taking into consideration the source pin and load pin of the net, the wiring processing method takes into account the reflection of electrical signals at the load pin and connects the load pin to the load pin. By reflecting the wiring length in the wiring cost, the branch point can be placed as close to the load pin as possible, which has the effect of reducing the maximum net delay time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a wiring processing method in a CAD system of the present invention.

FIG. 2 is a diagram showing a state in which a forward search using the maze method is performed using an unconnected load pin as a starting point and targeting a wiring pattern.

FIG. 3 is a diagram showing costs on a wiring pattern connecting each point in FIG. 2;

FIG. 4 is a diagram showing a comparison between the wiring pattern obtained according to FIG. 3 and the wiring pattern obtained using the conventional technique.

[Explanation of symbols]

101 Control means 102 Costing means 103 Wiring means 104 Memory means 201 Source pin 202 Load pin 203 Load pin 207-209 Wiring pattern 210, 211 Branching point

Claims (3)

[Claims] Claim 1: A wiring processing method in a CAD system when wiring nets with a fanout exceeding 1 in wiring design including LSI and printed circuit boards, comprising: (A) logical information and block placement information; storage means for storing terminal position information for each block; (B) for a wiring pattern connecting a source pin of a target net and a first load pin, an electrical signal from the source pin is reflected by the first load pin; Taking this into consideration, the cost is assigned to each point on the pattern to generate the first costing data, and then the cost is assigned from the second load pin to each point on the wiring pattern to generate the second costing data. Generating costing data, then summing the first costing data and the second costing data, and determining the point with the minimum total cost as a branching point from the wiring pattern to the second load pin. (C) a cost estimation means for sequentially determining branching points from the wiring pattern to the remaining load pins for the remaining load pins; wiring means for wiring a wiring pattern between the two, and then wiring a wiring pattern branched from the wiring pattern to each load pin based on branch point information for each load pin determined by the costing means, Determining the positions of the source pin and the number of load pins of the target net from the logic information of the storage means, the block arrangement information, and the terminal position information for each block, respectively;
The first load pin is selected from among the load pins according to predetermined criteria, and a wiring pattern between the source pin and the first load pin and a wiring pattern branched from the wiring pattern to each of the remaining load pins. C, characterized in that it is configured to wire
Wiring processing method in AD system. 2. The wiring processing method in a CAD system according to claim 1, wherein the costing means performs costing from the second load pin to each point on the wiring pattern and generates second costing data. A wiring processing method in a CAD system, characterized in that when generating the wiring pattern, a forward search is performed from the second load pin to each point on the wiring pattern using a maze method of a wiring algorithm. 3. In the wiring processing method in a CAD system according to claim 1, when the wiring means routes the wiring pattern branching from the wiring pattern to each load pin, the wiring processing method uses a maze method of a wiring algorithm to route the wiring pattern from the branching point to each load pin. A wiring processing method in a CAD system characterized by performing a backward search to each load pin.