JPH0434744U - - Google Patents

Info

Publication number
JPH0434744U
JPH0434744U JP1990075938U JP7593890U JPH0434744U JP H0434744 U JPH0434744 U JP H0434744U JP 1990075938 U JP1990075938 U JP 1990075938U JP 7593890 U JP7593890 U JP 7593890U JP H0434744 U JPH0434744 U JP H0434744U
Authority
JP
Japan
Prior art keywords
semiconductor device
lead frame
heat dissipation
view
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990075938U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990075938U priority Critical patent/JPH0434744U/ja
Publication of JPH0434744U publication Critical patent/JPH0434744U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示すもので、ａは
リードフレームの要部平面図、ｂは同上の半導体
装置が実装された要部平面図、ｃは同上の側面図
、第２図は従来の半導体装置の一例を示すもので
、ａはリードフレームの平面図、ｂは 同上の側
面図、ｃは同上の要部平面図、ｄは同上の半導体
装置が実装された要部平面図、ｅは同上の樹脂が
モールドされた平面図、ｆは同上の側面図を示す
ものである。 １，２……半導体装置、４……リードフレーム
、４ａ……リードフレーム、６……放熱板。 FIG. 1 shows an embodiment of the present invention, in which a is a plan view of the main part of a lead frame, b is a plan view of the main part on which the above semiconductor device is mounted, c is a side view of the above, and FIG. 1 shows an example of a conventional semiconductor device, where a is a plan view of a lead frame, b is a side view of the same as above, c is a plan view of the main part of the same as above, and d is a plan view of the main part of the same semiconductor device mounted on it. , e shows a plan view of the molded resin, and f shows a side view of the same. 1, 2... Semiconductor device, 4... Lead frame, 4a... Lead frame, 6... Heat sink.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 発熱量の大きい半導体装置のリードフレームへ
の実装構造において、リードフレームの少なくと
も半導体装置の実装部の裏面側に、放熱性に優れ
かつ絶縁性を有する放熱板を接着すると共に、前
記リードフレームの表面に半導体装置を実装した
ことを特徴とする半導体装置の実装構造。 In a structure in which a semiconductor device that generates a large amount of heat is mounted on a lead frame, a heat dissipation plate having excellent heat dissipation and insulation properties is bonded to at least the back side of the mounting part of the semiconductor device of the lead frame, and the surface of the lead frame is A mounting structure for a semiconductor device, characterized in that a semiconductor device is mounted on a semiconductor device.
JP1990075938U 1990-07-17 1990-07-17 Pending JPH0434744U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990075938U JPH0434744U (en) 1990-07-17 1990-07-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990075938U JPH0434744U (en) 1990-07-17 1990-07-17

Publications (1)

Publication Number Publication Date
JPH0434744U true JPH0434744U (en) 1992-03-23

Family

ID=31616957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990075938U Pending JPH0434744U (en) 1990-07-17 1990-07-17

Country Status (1)

Country Link
JP (1) JPH0434744U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014096432A (en) * 2012-11-08 2014-05-22 Mitsubishi Materials Corp Substrate for power module with copper plate and method for manufacturing substrate for power module with copper plate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014096432A (en) * 2012-11-08 2014-05-22 Mitsubishi Materials Corp Substrate for power module with copper plate and method for manufacturing substrate for power module with copper plate

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