JPH0459949U - - Google Patents

Info

Publication number
JPH0459949U
JPH0459949U JP1990102439U JP10243990U JPH0459949U JP H0459949 U JPH0459949 U JP H0459949U JP 1990102439 U JP1990102439 U JP 1990102439U JP 10243990 U JP10243990 U JP 10243990U JP H0459949 U JPH0459949 U JP H0459949U
Authority
JP
Japan
Prior art keywords
semiconductor element
heat radiation
heat sink
semiconductor device
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990102439U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990102439U priority Critical patent/JPH0459949U/ja
Publication of JPH0459949U publication Critical patent/JPH0459949U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例である半導体装置
の断面図、第２図ｂは第１図の半導体素子の一実
施例を示す平面図、第３図は従来の半導体装置の
断面図、第４図ａ，ｂおよび第２図ａは従来の半
導体素子の平面図である。 図において、１は半導体素子、２は電極パツド
、３はダイパツド部、４は接着剤、５はリード
、６は金属細線、７はモールド樹脂、８は放熱フ
イン、９は接着剤、１０はヒートシンク、１１
は放熱用パツド、１２は突起物、１３はアクテイ
ブ領域を示す。なお、図中、同一符号は同一、又
は相当部分を示す。 FIG. 1 is a sectional view of a semiconductor device which is an embodiment of this invention, FIG. 2b is a plan view showing an embodiment of the semiconductor device of FIG. 1, and FIG. 3 is a sectional view of a conventional semiconductor device. FIGS. 4a and 4b and FIG. 2a are plan views of conventional semiconductor devices. In the figure, 1 is a semiconductor element, 2 is an electrode pad, 3 is a die pad part, 4 is an adhesive, 5 is a lead, 6 is a thin metal wire, 7 is a molding resin, 8 is a heat radiation fin, 9 is an adhesive, 10 is a heat sink , 11
12 is a heat dissipation pad, 12 is a protrusion, and 13 is an active area. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 放熱を必要とする半導体素子のパツケージにお
いて、前記半導体素子の表面に放熱用パツドを設
け、前記半導体素子表面側にヒートシンクを設置
して前記ヒートシンクと前記放熱用パツドとを金
属バンプ等を介して接合したことを特徴とする半
導体装置。 In a package of a semiconductor element that requires heat radiation, a heat radiation pad is provided on the surface of the semiconductor element, a heat sink is installed on the surface side of the semiconductor element, and the heat sink and the heat radiation pad are bonded via a metal bump or the like. A semiconductor device characterized by:
JP1990102439U 1990-09-28 1990-09-28 Pending JPH0459949U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990102439U JPH0459949U (en) 1990-09-28 1990-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990102439U JPH0459949U (en) 1990-09-28 1990-09-28

Publications (1)

Publication Number Publication Date
JPH0459949U true JPH0459949U (en) 1992-05-22

Family

ID=31846695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990102439U Pending JPH0459949U (en) 1990-09-28 1990-09-28

Country Status (1)

Country Link
JP (1) JPH0459949U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018181871A1 (en) * 2017-03-31 2018-10-04 株式会社村田製作所 Module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018181871A1 (en) * 2017-03-31 2018-10-04 株式会社村田製作所 Module
CN110476245A (en) * 2017-03-31 2019-11-19 株式会社村田制作所 module
JPWO2018181871A1 (en) * 2017-03-31 2020-01-23 株式会社村田製作所 module
US11177189B2 (en) 2017-03-31 2021-11-16 Murata Manufacturing Co., Ltd. Module including heat dissipation structure

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