JPH0434748U - - Google Patents
Info
- Publication number
- JPH0434748U JPH0434748U JP7637990U JP7637990U JPH0434748U JP H0434748 U JPH0434748 U JP H0434748U JP 7637990 U JP7637990 U JP 7637990U JP 7637990 U JP7637990 U JP 7637990U JP H0434748 U JPH0434748 U JP H0434748U
- Authority
- JP
- Japan
- Prior art keywords
- pull
- resistor
- semiconductor integrated
- integrated circuit
- mos transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク回路図、
第２図は従来の半導体集積回路装置のブロツク構
成図である。
１，２……ＰチヤネルＭＯＳトランジスタ（プ
ルアツプ抵抗）、３，４，５……ＮチヤネルＭＯ
Ｓトランジスタ（プルダウン抵抗）、６……入力
バツフア回路、７……出力バツフア回路、８，９
……インバータ回路、１０……電源端子、２０…
…接地端子、１１，１２，２１，２２……入力端
子、３１，３２……出力端子、４１……試験用端
子、５０……内部論理回路、６０……試験用回路
。
FIG. 1 is a block circuit diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of a conventional semiconductor integrated circuit device. 1, 2...P channel MOS transistor (pull-up resistor), 3, 4, 5...N channel MO
S transistor (pull-down resistor), 6... Input buffer circuit, 7... Output buffer circuit, 8, 9
...Inverter circuit, 10...Power terminal, 20...
...Ground terminal, 11, 12, 21, 22... Input terminal, 31, 32... Output terminal, 41... Test terminal, 50... Internal logic circuit, 60... Test circuit.
Claims (1)
構成されるプルアツプ抵抗やプルダウン抵抗を備
えた相補型ＭＯＳトランジスタで構成したマスタ
ースライス方式の半導体集積回路装置において、
前記プルアツプ抵抗およびプルダウン抵抗を構成
するＭＯＳトランジスタを導通状態および遮断状
態に切り替える試験用回路を備えることを特徴と
する半導体集積回路装置。 ２ 試験用回路は、プルアツプ抵抗およびプルダ
ウン抵抗を構成するＭＯＳトランジスタのゲート
電圧を制御するように構成してなる実用新案登録
請求の範囲第１項記載の半導体集積回路装置。[Scope of Claim for Utility Model Registration] 1. In a master slice type semiconductor integrated circuit device configured with complementary MOS transistors having pull-up resistors and pull-down resistors configured with MOS transistors at input terminals and output terminals,
A semiconductor integrated circuit device comprising a test circuit for switching MOS transistors constituting the pull-up resistor and pull-down resistor into a conductive state and a cut-off state. 2. The semiconductor integrated circuit device according to claim 1, wherein the test circuit is configured to control the gate voltage of a MOS transistor constituting a pull-up resistor and a pull-down resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7637990U JPH0434748U (en) | 1990-07-18 | 1990-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7637990U JPH0434748U (en) | 1990-07-18 | 1990-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0434748U true JPH0434748U (en) | 1992-03-23 |
Family
ID=31617796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7637990U Pending JPH0434748U (en) | 1990-07-18 | 1990-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434748U (en) |
-
1990
- 1990-07-18 JP JP7637990U patent/JPH0434748U/ja active Pending
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