JPH04348519A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform the longitudinal micronization of a semiconductor device by patterning the silicon film made on the surface of a gate oxide film, and oxidizing the surface of this silicon film, and then, replacing the silicon film with a W film using Si reductive action by WF6 gas so as to form a W gate electrode. CONSTITUTION:A gate oxide film 2 is made on the surface of an Si substrate by thermal oxidation. Next, a polysilicon film 3 is stacked on the surface of the gate oxide film 2 by low-pressure vapor growth method. The polysilicon film 3 is patterned using photolithography method and dry etching method so as to form a polysilicon film 3a. Then, it is soaked in hot NHO3 liquid so as to oxidize the surface of the polysilicon film 3a. Subsequently, most part of the polysilicon film 3a is replaced with a W film 6, using the Si reductive action by WF6 gas. The W film 6 becomes a gate electrode. With the W film 6 as a mask, ions of impurities are implanted into the Si substrate 1 so as to form a source and drain region 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS transistor using a W film as a gate electrode.

0002

2. Description of the Related Art A conventional method for manufacturing a silicon gate type MOS transistor will be described with reference to sectional views showing the steps shown in FIG.

First, a gate oxide film 2 with a thickness of several tens of nanometers is formed on the surface of the Si substrate 1 by thermal oxidation [FIG. 3(A)].
. Next, a polysilicon film 3 with a thickness of 400 to 600 nm is deposited on the surface of the gate oxide film 2 by low-pressure vapor deposition, and impurities are diffused into the polysilicon film 3 to reduce the sheet resistance of the polysilicon film 3 (see FIG. 3). B)]. Subsequently, the polysilicon film 3 is patterned using photolithography and dry etching techniques to form a polysilicon film 3a that will become a gate electrode [FIG. 3(C)]. Subsequently, the Si substrate 1 is deposited using the polysilicon film 3a as a mask.
Then, impurity ions are implanted, and heat treatment is performed in an inert gas atmosphere at 900 to 1000° C. to form source/drain regions 4 [FIG. 3(D)].

However, as the gate oxide film 2 becomes thinner with the progress of miniaturization of semiconductor devices, penetration of the gate oxide film 2 by impurities in the polysilicon film 3a, which is the gate electrode, occurs, and the electrical characteristics deteriorate. The impact on this cannot be ignored. Therefore, it is necessary to reduce the concentration of impurity diffusion into the polysilicon film 3. In this case, the sheet resistance of the polysilicon film 3a increases, which in turn causes a decrease in the operating speed of the semiconductor device and an increase in the amount of heat generated. FIG. 5 shows the dependence of the sheet resistance of the polysilicon film 3 on the polysilicon film thickness under certain phosphorus diffusion conditions. As is clear from the figure, as the size of the polysilicon film 3 increases due to miniaturization,
As the thickness of the polysilicon film becomes thinner, the sheet resistance increases in inverse proportion to the thickness of the polysilicon film, further exacerbating the above-mentioned problems.

[0005] For this reason, in recent years, the miniaturization of semiconductor elements,
As a means to meet the demand for higher speeds, a polycide gate type MOS transistor formed by a manufacturing method as shown in the cross-sectional view of the process sequence in FIG. 4 has been adopted.

In this method, first, 2
A gate oxide film 2 having a thickness of approximately 0 nm is formed by thermal oxidation [FIG. 4(A)]. Next, a polysilicon film 3 with a thickness of 150 to 200 nm is deposited on the surface of the gate oxide film 2 by low pressure vapor deposition.
m is deposited and an appropriate amount of impurity is diffused into the polysilicon film 3 [FIG. 4(B)]. After that, WS was formed by sputtering method.
The i film 5 is formed to a thickness of about 150 to 200 nm [FIG. 4(C)
]. Subsequently, the WSi film 5 and polysilicon film 3 are patterned using photolithography and dry etching to form the WSi film 5a, which will become the gate electrode.
A polysilicon film 3a is formed [FIG. 4(D)]. Subsequently, impurity ions are implanted into the Si substrate 1 using the WSi film 5a and the polysilicon film 3a as masks.
A heat treatment is performed in an inert gas atmosphere at 00 to 1000° C. to form the source/drain regions 4, and at the same time, the WSi film 5a is annealed [FIG. 4(E)].

The sheet resistance of the gate electrode made of the WSi film 5a and the polysilicon film 3a obtained by this method is about 5Ω/□.

[0008]

[Problems to be Solved by the Invention] However, in the polycide gate type MOS transistor manufactured by the above manufacturing method,
During the dry etching for forming the gate electrode, the WSi film 5 and the polysilicon film 3, which are dissimilar films, must be etched at the same time, so it is important to set etching conditions that provide a good etched shape and dimensional accuracy. Have difficulty. Further, since the polysilicon film 3 has a considerably higher resistivity than the WSi film 5, it does not contribute much to electrical conduction and acts as a factor for inhibiting vertical miniaturization.

[0009]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate oxide film on the surface of a semiconductor substrate, a step of depositing a silicon thin film by a low pressure vapor phase epitaxy method, and a step of using a photolithography technique. A process of processing a silicon thin film into a fine pattern using dry etching technology, a process of oxidizing the surface of the silicon thin film processed into a fine pattern, and a process of converting the silicon thin film whose surface has been oxidized using a Si reduction reaction using WF6 gas into a W thin film. and a step of implanting impurity ions using the W thin film as a mask.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a cross-sectional view of the process order for explaining the first embodiment of the present invention.

First, as shown in FIG. 1A, a gate oxide film 2 having a thickness of approximately 20 nm is formed on the surface of a Si substrate 1 by thermal oxidation. Next, as shown in FIG. 1B, a polysilicon film 3 is deposited to a thickness of 150 to 200 nm on the surface of the gate oxide film 2 by low pressure vapor phase epitaxy. Next, as shown in FIG. 1C, the polysilicon film 3 is patterned using photolithography and dry etching techniques to form a polysilicon film 3a. After that, heat H
The surface of the polysilicon film 3a is coated with 11
~15 angstroms are oxidized. Next, Figure 1 (
As shown in D), most of the polysilicon film 3a is replaced with a W film 6 using a Si reduction reaction using WF6 gas. The W film 6 becomes a gate electrode. Subsequently, Figure 1(E)
As shown in FIG. 2, impurity ions are implanted into the Si substrate 1 using the substituted W film 6 as a mask.
Heat treatment is performed in an inert gas atmosphere at .degree. C. to form source/drain regions 4.

The above-mentioned replacement of the polysilicon film 3a with the W film 6 using the Si reduction reaction using the WF6 gas is performed at 1To
In a reduced pressure atmosphere around rr, the partial pressure of WF6 gas diluted with an inert gas is controlled to several to several mTorr, and Si
This is done by heating the substrate 1 to 300° C. for about 30 minutes.

[0013] Furthermore, the surface oxidation of about 11 to 15 angstroms of the polysilicon film 3a prior to the Si reduction reaction by WF6 gas is caused by submergence into the hot HNO3 solution.
Another chemical treatment, e.g. NH4 OH + H2O2 + H2
This can also be achieved by submersion in an O solution. For more precise oxide film thickness control, polysilicon film 3a
It is also effective to remove the natural oxide film on the surface of the polysilicon film 3a using a diluted HF solution immediately before the surface oxidation of the polysilicon film 3a. However, in this case, it is desirable to suppress the etching amount of the natural oxide film to 50 angstroms or less so as not to remove too much of the gate oxide film 2 covering the Si substrate 1. The surface oxidation of the polysilicon film 3a can also be performed by thermal oxidation using dry O2 gas. However, in this case,
Replacement of polysilicon film 3a with W film 6 using Si reduction reaction using WF6 gas must be performed by heating Si substrate 1 to 450° C. or higher.

WF6 of the polysilicon film 3a described above
The replacement with W film 6 using Si reduction reaction with gas was reported by Kobayashi et al. in Monthly Semiconductor World (Monthly Semiconductor World).
emiconductor World) April issue, 1989, pages 37-42.
W is usually suppressed by replacing it with a W film of about 10 nm.
The Si reduction reaction using F6 gas is performed by forming a thin oxide film on the surface of the polysilicon film, thereby making it possible to replace the polysilicon film with a W film down to the micrometer level.

The W film 6 formed in this example is slightly porous and has a specific resistance of 70 to 120 μΩcm, and the sheet resistance of the W film 6 with a thickness of 200 nm is 3.6 to 6.
Ω/□, which is comparable to the sheet resistance of a conventional polycide gate. When the polysilicon film 3a is replaced with the W film 6, some variation occurs in pattern dimensions, but this is at a level that poses no problem in fine patterns.

Although this embodiment has been described using a polysilicon film as an example, an amorphous silicon film may be used instead of the polysilicon film. In addition, after the replacement of the polysilicon film 3a with the W film 6, H2 gas is introduced for a short time instead of the inert gas for diluting the WF6 gas, and a selective vapor phase growth method of W using the H2 reduction reaction is performed. If the surface of the W film 6 is covered with a thickness of about 10 nm, the W film 6 will be covered during the impurity ion implantation to form the source/drain regions 4.
This further improves maskability.

FIG. 2 is a sectional view showing the order of main steps for explaining a second embodiment of the present invention. This example is the same as the first example up to the step shown in FIG. 1(D) in the first example.

After replacing the polysilicon film with the W film 6 by the Si reduction reaction using the WF6 gas, ions of low concentration impurities are implanted into the Si substrate 1 using the W film 6 as a mask, as shown in FIG. 2(A). Then, a heat treatment is performed in an inert gas atmosphere at 900 to 1000° C. to form a low concentration junction region 7. Next, as shown in FIG. 2(B), WF6 +H2
H2 reduction reaction of WF6 by gas, or WF
A W film 8 with a thickness of about 150 to 200 nm is additionally grown on the surface of the W film 6 by a W selective vapor phase growth method using a SiH4 reduction reaction of WF6 with 6 +SiH4 gas. Subsequently, as shown in FIG. 2C, impurity ions are implanted into the Si substrate 1, and heat treatment is performed in an inert gas atmosphere at 900 to 1000° C. to form source/drain regions 4.

In this embodiment, an MO of an LDD structure can be easily formed by simply adding a W selective vapor phase growth process using an H2 reduction reaction or a SiH4 reduction reaction to the first embodiment.
It has the advantage that an S transistor can be formed.

[0020]

As explained above, the present invention provides a method for manufacturing a semiconductor device in which a silicon thin film formed on the surface of a gate oxide film is processed into a pattern, the surface of the silicon thin film is oxidized, and then WF6 gas is applied. By replacing the silicon thin film with a W thin film using a Si reduction reaction and forming a MOS transistor with a W gate electrode, the sheet resistance of the gate electrode can be maintained at a low resistance value of about 5Ω/□ while the vertical direction of the semiconductor device can be improved. This has the effect of enabling direction miniaturization. Furthermore, because only a single layer and a thin silicon thin film is processed, it is possible to achieve high integration in minute dimensions.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device.

FIG. 4 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device.

FIG. 5 is a graph for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

1 Si substrate 2 Gate oxide film 3, 3a Polysilicon film 4 Source/drain region 5,5a WSi film 6,8 W film 7 Low concentration junction area

Claims (1)

[Claims] 1. A step of forming a gate oxide film on the surface of a semiconductor substrate, a step of depositing a silicon thin film by low pressure vapor phase epitaxy, and processing the silicon thin film into a fine pattern by photolithography technology and dry etching technology. a step of oxidizing the surface of the silicon thin film processed into a fine pattern, and a step of oxidizing the surface of the silicon thin film processed into a fine pattern;
Manufacturing a semiconductor device comprising the steps of replacing the silicon thin film whose surface has been oxidized with a W thin film using a reduction reaction, and implanting impurity ions using the W thin film as a mask. Method.