JPH0435108B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention receives text broadcasting transmitted superimposed on the vertical blanking period of a video signal of television broadcast radio waves, and displays text and text on a display device such as a cathode ray tube.
The present invention relates to a coded transmission teletext receiving device that displays a graphic screen. [Prior Art] An example of a conventional device of this type is shown in FIG. In the figure, reference numeral 1 denotes an antenna for receiving television broadcast waves, and a character signal is superimposed on the vertical blanking period of the video signal of the television broadcast waves. The character signal passes from the antenna 1 to the tuner 2, is detected by the intermediate frequency amplification circuit 3, and is extracted by the character signal extraction circuit 7. The extracted character signals are temporarily stored in a buffer memory 8, and only the necessary character signals are decoded by a central control unit (hereinafter referred to as CPU) 9 and sent to a display memory 11 via a display control circuit 10.
is stored in 4 is a video amplification circuit that receives the output of the intermediate frequency amplification circuit 3; 5 is an output interface circuit connected to the output side of the video amplification circuit 4; this output interface circuit 5 is a cathode ray tube (CRT);
This is an interface for switching between displaying the video signal from the video amplifying circuit 4 or displaying the teletext read out from the display memory 11 and converting the level when displaying the video signal on the video amplification circuit 6. 12 is a program selection device, 13 is a program
ROM 15 is a character font ROM, which decodes character signals and generates characters and figures. 14 is for work
RAM 16 is an error correction circuit, and this error correction circuit 16 has a function of correcting a code error in a character signal. These are connected to the CPU 9 via a bus. FIG. 5 is a diagram showing a display screen on a television. In the figure, numeral 17 indicates a television screen, and the number of pixels is 248 pixels in the horizontal direction 18 and 204 pixels in the vertical direction 19.
(horizontal) x 204 (vertical), 248 from the top of the screen.
The range of (horizontal) x 12 (vertical) is the page header (PH). FIG. 6 is an explanatory diagram showing the functional blocks displayed on the CRT 6 shown in FIG. 4. Functions such as coloring, flashing, and concealment are displayed using this functional block as a unit, and the number of pixels constituting the minimum unit of the functional block is is 4 (horizontal) x 4 (vertical). And when displaying this function block, 4Tc (1Tc)
The number of bits of pixel information required within 0.1746 μs (period of 1/364 of the horizontal synchronizing pulse) is 15 bits in total, as shown in Table 1 below. However, the number of data required to display 16-pixel data of 4 (horizontal) x 4 (vertical) functional blocks is 16 bits of text/figure information, 4 bits of text/figure color, and 4 bits of text/figure background color. , 3 bits of functional block information are required, and 4 pixels in the vertical direction (4
Between lines), only the character/graphic information changes, and the other image information may be the same data.

[Table] FIG. 7 is an explanatory diagram showing two minimum functional blocks displayed on the CRT 6 of FIG. 4, and shows the image information required within 8Tc. Table 2 below shows the number of bits of pixel information required. In this case, as shown in Table 2 below, a total of 30
A display memory 11 showing bit image information as shown in FIG.
It is necessary to read it from.

[Problem that the invention seeks to solve]

However, the encoded transmission type teletext receiving apparatus as shown in FIG. 4 has the following problems. That is, when character/graphic information, color information, and functional block information are completely or incompletely separated into separate display memories, that is, when the display memory bus exceeds 8 bits, the display control circuit 10 Image information can be read out from the memory 11 slowly over time, and even while information from the display memory 11 is being displayed, it is possible to write to the display memory 11 or read out other information.
This has the disadvantage that the number of address pins, memory I/O pins, etc. provided to the display memory 11 increases, which increases the cost of the display memory 11 and wastes a lot of display memory space. This is particularly unsuitable when implementing the display control circuit 10 into an LSI, since the number of pins is large. Furthermore, if the memory bus is read out in 8 bits without separating the image information in the display memory 11, the configuration of the display control circuit 10 becomes complicated, and there is no time margin. The problem is that it is technically difficult to write to or read from. The present invention has been made to solve these problems, and its purpose is to facilitate the configuration of a display control circuit, use the memory space of the display memory efficiently, and reduce costs. Teletext reception is a coded transmission method that allows for a reduced number of control signals from the display control circuit to the display memory, and allows arbitrary writing to or reading from the display memory even during display. It provides equipment. [Means for Solving the Problems] The encoded transmission type teletext receiving device according to the present invention includes a display memory that stores each piece of image information given regular addresses, and a display memory that stores each image information given a regular address, and a display memory that stores each image information given a regular address, An address conversion circuit for converting information addresses and functional block information addresses, a time division control circuit for time division switching control between display only addresses and write and read only addresses, and writing to display memory during display or, for example, a CPU. The display memory has a timing generation circuit that generates write and read timings to read out data necessary for the display, and a display control circuit that controls writing and reading of the display memory. [Operation] In this invention, when reading out each image information stored in the display memory and displaying it on the display device,
The address conversion circuit automatically converts and reads color information and functional block information from the address of character/graphic information, and at the same time writes data to the display memory or reads data necessary for the CPU. possible. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a coded transmission type teletext receiving apparatus according to an embodiment of the present invention, showing only the portions related to the present invention, that is, the portions surrounded by the dashed line in FIG. In this FIG. 1, 20 is a dynamic RAM (hereinafter referred to as a
The DRAM used as the display memory 20 is 64K x 8 so that the storage surface can be configured with 4 screens, or 16K x 8 or 64K x 2 (however, 64K in this case is 4-bit output). )
It is configured so that the memory surface can be configured as one screen. Note that "8", "5", and "3" in the figure each indicate the number of bits. Each circuit except this display memory 20 is provided in the display control circuit 10 shown in FIG.
21 is a display-only vertical counter consisting of 8 bits Y ₀ to _{Y 7} and used to determine the position of the 204 scanning lines in the vertical direction of the television; 29 is a write counter consisting of 8 bits; A read-only vertical counter 22 is an address conversion circuit that receives the output of the vertical counter 21 as an input and converts text/graphic information addresses to color information and function block information addresses when reading from the display memory 20. be. Further, 30 is a time division control circuit, which is the output 8 of the address conversion circuit 22.
bits and the output 8 bits of the write/read only vertical counter 29 within a certain period (8Tc
(internal)) is time-divisionally controlled. 23 is a display memory address circuit having a switching function for providing a row address and a column address to the display memory (DRAM) 20. In addition, AB in the figure indicates 8 from this display memory address circuit 23 to the display memory 20.
This is the bit address bus. 24 is a timing generation circuit, which is the third
11.45MHz reference clock CLK as shown in Figure a
Based on, various timing clocks C1 to C9
is generated. Here the frequency is 11.45MHz
is twice the frequency of 1Tc = 0.1746 μs (1/365 period of the horizontal synchronization pulse). 25 is a horizontal counter that consists of 5 bits and handles the 248 pixels in the horizontal direction of the television with 31 bytes for every 8 bits, and is always aligned with the horizontal scanning line of the television (actually the display area). It is configured. The horizontal counter 25 also functions as a refresh counter for the display memory 20, which is a DRAM. 26 is a display memory address control circuit that controls the address of the display memory, that is, the address of multiple screens with 3 bits.The reason why this is set to 3 bits is that in the case of a DRAM with a capacity of 64K, each row address and column address are Since it is given in 8 bits, the address information is 16 bits in total, but since the outputs of the vertical counters 21 and 29 and the horizontal counter 25 are 8 bits and 5 bits, respectively,
(16-8-5) becomes 3 bits. however,
In the case of 16K, row and column addresses each have 7 bits. In addition, in the case of this example, a maximum of 4
Up to the screen. 27 are row address strobe signals and column address strobe signals to the display memory 20;
and a display memory control circuit for providing control signals such as write signals. Reference numeral 28 is a display memory input/output circuit composed of 8 bits and connected to the display memory 20 by a memory bus MB for exchanging image information. In this embodiment, each image information of character/graphic information and color information/functional block information is stored in the display memory 20 by the display memory address circuit 23, given regular addresses, and when read, That is, during display, the address conversion circuit 22
The color information and functional block information are automatically converted into addresses and read out from the addresses of character/graphic information. Further, each of the above circuits is controlled by a timing signal from the timing generation circuit 24, and even when data in the display memory 20 is being displayed, the time division control circuit 30 writes or writes data to the display memory 20. Reading can be performed arbitrarily as long as the period is longer than a certain period. Next, the operation will be explained. First, an example of converting the text/figure information address to be given to the display memory 20 into first and second color information (including text/figure color and text/figure background color, respectively) and function block address is shown in Table 3 below. This is shown and explained below. Note that this is a case of hexadecimal display.

【table】

【table】

〔Effect of the invention〕

As described above, according to the present invention, the display control circuit includes an address conversion circuit for converting character/graphic information addresses, color information addresses, and functional block information addresses, and also includes an address conversion circuit for converting character/graphic information addresses, color information addresses, and functional block information addresses, and a Since a time division control circuit and a timing generation circuit are provided to enable writing and reading, the configuration of the display control circuit is simplified, and
This has the effect that the memory space of the display memory can be used efficiently and costs can be reduced. Furthermore, since writing to or reading from the display memory is possible even during screen display, there is an effect of increasing the display speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a coded transmission type teletext receiving device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the address conversion operation in the device, and FIG. 3 is a diagram of the device. FIG. 4 is a timing chart diagram for explaining the operation; FIG. 4 is a schematic block diagram of a conventional encoded transmission type teletext receiving device; FIG.
7 to 7 are diagrams for explaining the operation of the conventional device, in which FIG. 5 is a diagram showing a display screen on a television, FIG. 6 is a diagram showing functional blocks displayed on a CRT, and FIG. The figure shows two minimum functional blocks displayed on a CRT. 6... Cathode ray tube (display device), 10... Display control circuit, 20... Display memory, 21... Display-only vertical direction counter, 22... Address conversion circuit,
24...timing generation circuit, 29...writing,
Read-only vertical counter, 30...time division control circuit.

Claims (1)

[Scope of Claims] 1. Coded transmission that receives a coded transmission character broadcast that is sent out superimposed on the vertical blanking period of a video signal of a television broadcast radio wave, and displays a character/graphic screen on a display device. In the teletext receiving device, each screen information is stored with regularity.
Display memory consisting of DRAM and reading from display memory are 8Tc (Tc=
A display control circuit that controls the page mode read cycle in which a row address strobe signal is applied four times and then a column address strobe signal is applied four times during a period of 5.73 MHz), and a character/graphic information address to be applied to the display memory. an address conversion circuit that converts the color information address and the functional block address; an 8-bit memory bus for exchanging image information between the display memory and the display control circuit; and an 8-bit memory bus that displays the image information in the display memory. a time-sharing control circuit that controls and outputs display-only addresses for writing and reading each image information to and from the above-mentioned display memory in a time-sharing manner; A coded transmission type teletext receiving apparatus comprising a timing generation circuit that generates a timing for writing or reading image information into the display memory.