JPH0435366A - Vertical screen position adjustment circuit - Google Patents

Abstract

PURPOSE:To surely erase a white level display in the blanking period earlier than a delayed vertical synchronizing signal by providing a vertical synchroniz ing signal delay circuit and outputting a vertical synchronizing signal earlier timewise by one period of a horizontal synchronizing signal than the delayed vertical synchronizing signal to process the blanking. CONSTITUTION:The adjustment circuit is provided with a field detection circuit 6 and a vertical synchronizing signal delay circuit 7. The field detection circuit 6 detects a vertical synchronizing signal stays in an odd number field or an even number field and outputs a different output depending whether the vertical synchronizing signal stays in an odd number field or an even number field and the vertical synchronizing signal delay circuit 7 delays the vertical synchro nizing signal for a half of the horizontal scanning period at an even number field and gives the result to a vertical deflection circuit, from which a vertical synchronizing signal earlier timewise by one period of the horizontal synchroniz ing signal from the delayed vertical synchronizing signal is outputted. Thus, when the video signal is inverted to display brightly the background of a charac ter, the vertical blanking on the upper and lower parts of the screen is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical screen position adjustment circuit for adjusting the vertical screen position in an ink-lace type display monitor that displays the background of characters in white.

2. Description of the Related Art In recent years, digital display monitors that display the background of text in white have been widely used, but in order to display the background of text in white on such display monitors, the input video signal must be inverted and horizontally , so that the video signal is not displayed on the screen only during the vertical retrace period.

A conventional vertical screen position adjustment circuit will be described below with reference to the drawings.

FIG. 3 is a block diagram of a conventional vertical screen position adjustment circuit.

In FIG. 3, the vertical synchronizing signal is delayed by a monostable multivibrator 1 for a certain period of time to a certain position in the vertical R line period, thereby determining the vertical screen position. The delayed vertical synchronization signal is input to the vertical deflection circuit 2, and two signals are generated by the vertical deflection circuit 2, one of which is input to the vertical deflection coil in synchronization with the delayed vertical synchronization signal. , the other signal is input to the blanking circuit 4 as a vertical blanking signal synchronized with the delayed vertical synchronizing signal. The video symbol inversion circuit 5 inverts the black and white levels of the video signal, but if the video signal below the black level (during the blanking period) is directly inverted to the white level, it will be displayed white. At the output of , the video number 100 during the blanking period is again lowered to the black level and blanked.

Problem to be Solved by the Invention However, in the conventional configuration described above, since the monostable multivibrator 1 delays the vertical synchronization signal by a certain period of time regardless of the horizontal synchronization signal, blanking is performed by the output of the vertical blanking circuit 4. is sometimes applied during the horizontal scanning period, and in such a case, there is a problem in that an abnormal display occurs in which a portion of the video signal at the top and bottom of the screen is interrupted, as shown in FIG.

The present invention provides a vertical screen position adjustment circuit that can reliably perform vertical blanking at the top and bottom of the screen when the background of characters is displayed brightly by inverting a video signal using an interlace method.

Means for Solving the Problems In order to solve the above conventional problems, the vertical screen position adjustment circuit of the present invention detects whether the vertical synchronization signal is an odd field or an even field, and detects whether the vertical synchronization signal is an odd field or an even field. A field detection circuit that takes different outputs depending on whether the field is an odd field or an even field, and the vertical synchronization signal and the output of the field detection circuit are input, and the vertical synchronization signal is synchronized with the vertical synchronization signal. The vertical synchronization signal to be delayed is provided with a longest delay circuit, and the vertical synchronization signal delay circuit is configured to delay 1/1 of the horizontal scanning period during the even field.
The vertical synchronizing signal is delayed by a period of 2, and is applied to a vertical deflection circuit to output a vertical synchronizing signal that is temporally earlier than the delayed vertical synchronizing signal by one period of the horizontal synchronizing signal. It is.

According to the vertical screen position adjustment circuit of the present invention, the vertical synchronization signal delay circuit synchronizes and delays the vertical synchronization signal with the horizontal synchronization signal, so that the vertical synchronization signal is input during the horizontal scanning period and blanking is performed. It will never be done. Furthermore, the vertical synchronization @ signal delay circuit performs blanking by outputting a vertical synchronization signal that is temporally earlier than the delayed vertical synchronization signal by one period of the horizontal synchronization signal. The white display during the line period can be erased more quickly and reliably than by the delayed vertical synchronization signal. Further, since the vertical screen position adjustment circuit of the present invention is equipped with a field detection circuit that takes different outputs depending on whether the vertical synchronization signal is an odd field or an even field, when the vertical synchronization signal is an even field, In the case where the vertical synchronizing signal is delayed by 1/2 of the horizontal scanning period in the vertical synchronizing signal delay circuit according to the output of the field detection circuit and scanning is performed in an interlaced manner, the video signal can be correctly displayed on the screen.

Embodiment Hereinafter, a vertical screen position adjustment circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the vertical screen position adjustment circuit of the present invention;
FIG. 2 is a timing chart of the vertical screen position adjustment circuit of the present invention. In FIG. 2, synchronization signals for even and odd fields are expressed as (even) and (odd), respectively, to distinguish them.

In FIG. 1, 6 is a field detection circuit, and this field detection circuit 6 is a D-type 7-lip flop converter (hereinafter referred to as DFF) which uses a vertical synchronization signal as a clock and inputs a horizontal synchronization signal to produce an output Q. )6a.

The field detection circuit 6 also includes a resistor 6c, a diode 6b, and a capacitor 6d, which are provided at the front stage of the input of the DFF 6a to determine the time constant of the horizontal synchronization signal.

The resistor 6C and the diode 6b are connected in parallel with each other, and the capacitor 6d is connected in parallel with the horizontal synchronizing signal line input to the DFF 6a.

A resistor 6e and a capacitor 6f are connected in series and in parallel, respectively, to a line of a vertical synchronizing signal input as a clock of DFFea. The voltage of the output Q of the DFF 6a is applied to a diode 7h of a vertical synchronization signal delay circuit γ, which will be described later.

In the vertical synchronization signal delay circuit 7, the vertical synchronization signal is input as data to DFFyb, and the horizontal synchronization signal is input as a clock to DFF7b. DFF7b latches the vertical synchronization signal at the rising edge of the horizontal synchronization signal and generates an output.
This output is input to the shift register 7a. The horizontal synchronization head number 7a is input as a clock to the shift register 7a, and vertical synchronization signals Q1 and Q2 synchronized with the horizontal synchronization signal are output. The output Q1 is outputted one clock (one period of the horizontal synchronizing signal) earlier than the output Q2 and inputted to the vertical blanking circuit 4 as a vertical blanking signal. Also, the output Q1 and the output Q2 are input to the OR game) 7G, but the output Q of the field detection circuit 6 mentioned above is the output Q1.
By changing the conduction state of the diode 7h connected in parallel to the line connecting the gate and the OR gate 7, the rise of the output Q1 is caused by the change
delayed by f. This resistor 7e and capacitor 7
f has a value that delays the output of the OR gate by ten horizontal scanning periods. The output of the OR gate 7 is input to a vertical deflection circuit 8, and the output of the vertical deflection circuit 8 is input to a vertical deflection coil. The output of the vertical blanking circuit 4 erases the white display during the blanking period that occurs when the video signal is inverted by the video signal inverting circuit 6.

The operation of the vertical screen position adjustment circuit of this embodiment configured as described above will be explained below.

In the signal waveform diagram of Fig. 2, the maximum amplitude of each signal is all 1V, and the shift register 7a, DFF7b, D
The threshold level of the clock (also H gate) of F F 6 a and the OR gate 7q is set to H+■.

In Fig. 1, when a horizontal synchronizing signal is input to the field detection circuit 6, when the horizontal synchronizing signal rises, the diode 6
b is biased in the forward direction and the capacitor 6d is rapidly charged, resulting in a horizontal synchronization signal with a sharp rise as shown in FIG. 2(d), which is input to the DFF 6a. Next, when the horizontal synchronization signal falls from high level to low level, the diode 6b is reverse biased9, and the charge stored in the capacitor 6d is slowly discharged by the resistor 6C, so that the horizontal synchronization signal falls. Becoming dull.

Therefore, since the discharging time is longer than the charging time, the high level period of the horizontal synchronizing signal, which generally has a short high level pulse width, can be lengthened and input to the DFF 6a. In addition, the phase of the vertical synchronization signal is slightly delayed from that of the data (vertical synchronization signal) due to the phase shift circuit composed of a resistor 6e and a capacitor 6f, so when the vertical synchronization signal rises as a clock pulse of the DFF 6a, D F F 6 The state of the data can be reliably read using a. The output Q of D F F 6 a is Ov when the vertical synchronization signal is an odd field.
, if the vertical synchronization signal is an even field, it becomes 1v. This output Q becomes 1v as shown in Fig. 2(q) at the same time as the clock of DFF6a becomes 17 or more in Fig. 2(e) in an odd number field, and as shown in Fig. 2(h) in an even number field. In the case of an odd number field, Ov is delayed by ten horizontal scanning periods. This output Q biases the diode 7h of the vertical synchronizing signal delay circuit 7 in the direction of around 1 in the odd field, and the output Q1 of the DFF 7a becomes Ov, and in the even field the diode 7h
h is biased in the opposite direction.

In the vertical synchronization signal delay circuit 7, the horizontal synchronization signal is connected to the resistor 7.
The phase of the horizontal synchronization signal is slightly delayed by the phase shift circuit constituted by C and the capacitor 7d, and this horizontal synchronization signal becomes the clock pulse of DFFyb. D
The clock of the horizontal synchronization signal and the vertical synchronization signal as shown in FIG. 2(i) are input to the FF7b, and this DFF7
b latches the vertical synchronization signal at the rising edge of the horizontal synchronization signal and outputs a vertical synchronization signal synchronized with the horizontal synchronization signal.

Therefore, this output is exactly 1 in the odd field and even field as shown in Figure 2 (i) and Figure 2 □□□).
The signals are input to the shift register 7a with a time shift of one clock (one period of the horizontal synchronizing signal). Shift register 7a
A horizontal synchronization signal is used as the clock, and the output (vertical synchronization signal) of the DFF 7b is input and delayed, and the vertical position of the screen is determined by the amount of delay. This delayed vertical synchronization signal is output as Ql, and this output Q1 is shown in FIG.
) and FIG. 2), the signals are input to the vertical blanking circuit 4 as vertical blanking signals with a difference of exactly one clock (one period of the horizontal synchronizing signal) between the odd and even fields. Also, the output Q1 is a resistor 7e and a capacitor 7f.
It passes through and becomes input B of OR gate 7q. Here, in the case of an odd field, the diode 7h is forward biased as described above, so the input B becomes O as shown in FIG. 2(r).
It becomes constant at V. In the case of an even field, as shown in Figure 2 (8), the waveform of the rising edge of input B is not dull, and this human input B reaches the threshold level when 10 horizontal scanning periods (+H) have elapsed from the rising edge. (+V),!
:Become.

The shift register 7a outputs an output Q2 which is delayed by one clock from the output Q1 as shown in FIG. 2(b) and FIG. 2(0), and this output Q2 is As shown in (b), it becomes the input A of the OR gate 7q. O
The R gate 7q outputs the logical sum of the output Q1 and the output Q2, but since the threshold level of the gate of this OR gate 7q is +V like the clocks of other DFFs, in the case of an even field, the threshold level of the gate of the OR gate 7q is +V, so in the case of an even field, the threshold level of the gate of the OR gate 7q is +V. As shown in FIG. 2, the output C is generated at the moment the input B in FIG. 2 (8) becomes +V. Here, in the case of an odd field, the input B becomes Ov as described above, so the output C is generated at the same time as the input A shown in FIG. 2(b) (see FIG. 2(1)). This output C is input to the vertical deflection circuit 8. Therefore, the timing of the rise of the output of the DFF 7b mentioned above differs by one clock (one period of the horizontal synchronizing signal) in even and odd fields, as shown in Figure 2 (0) and Figure 2 (k). , and finally, as can be seen by comparing Figure 2 (1) and Figure 2 Heng), the rise time of output C is 10 horizontal scanning periods (
+H). In this way, the output C is input to the vertical deflection circuit 2. The vertical deflection circuit 2 sends a deflection current synchronized with the output C to the deflection coil 3 to perform vertical deflection.

As described above, the output Q1 of the shift register 7a is output one clock (one cycle of the horizontal synchronizing signal) earlier than the output Q2 and inputted to the vertical blanking circuit 4 as a vertical blanking signal. The video signal inversion circuit 5 inverts the video signal, but if the video signal below the black level (during the blanking period) is inverted, it will remain on the screen as a white display, so this white display is caused by the vertical blanking signal cancellation circuit 5. The output is dropped below the black level and blanked. Therefore, the video signal during the blanking period is reliably erased.

As described above, the vertical screen position adjustment circuit of the present invention has a DF17
Since the vertical screen position is determined by outputting a vertical synchronizing signal synchronized with the horizontal synchronizing signal in step b and delaying the vertical synchronizing signal synchronized with the horizontal synchronizing signal in the shift register 7a, the screen as shown in FIG. There will be no abnormal display where a part of the image is cut off. Moreover, regarding the output of the shift register 7a, an output Q2 is generated and is ORed to the vertical deflection circuit 2.
Since the output Q1 is input to the vertical blanking circuit 4 earlier by one clock (one period of the horizontal synchronizing signal) of the shift register 7a than the output C of the gate 7q is input, the vertical blanking circuit Blanking at the time of video signal inversion by the output of No. 4 is performed earlier in time than vertical deflection. Therefore, blanking is performed reliably during the vertical blanking period. It's a trench, D.
Since the horizontal synchronization signal and the vertical synchronization signal are synchronized by FF7b, as shown in Fig. 2 (j) and (k), the rising edge 9 of the output of DFF7b during odd and even fields differs by exactly one clock. , the resistor 7e and the capacitor 7f cause the rise of the output C of the OR gate to deviate by exactly 10 horizontal scanning periods between odd and even fields, as shown in Figure 2 (1) and Figure 2 (u), so the interlace method is used. The video signal can be displayed accurately even if the

Effects of the Invention As described above, in the vertical screen position adjustment circuit of the present invention, the vertical synchronization signal delay circuit delays the vertical synchronization signal in synchronization with the horizontal synchronization signal, so that the vertical synchronization signal is input during the horizontal scanning period. No blanking occurs during the blanking period, and blanking is ensured during the blanking period. In addition, the vertical synchronization signal delay circuit performs blanking by outputting a vertical synchronization signal that is temporally earlier than the delayed vertical synchronization signal by one cycle of the horizontal synchronization signal, so the blanking that occurs when the video signal is inverted. The white display during the period can be quickly and reliably erased by the delayed vertical synchronization signal. Furthermore, the vertical screen position adjustment circuit of the present invention is equipped with a field detection circuit that takes different outputs depending on whether the vertical synchronization signal is an odd field or an even field. When the vertical synchronizing signal is delayed by 1/2 of the horizontal scanning period in the vertical synchronizing signal delay circuit based on the output of the detection circuit and an interlaced system is used, the video signal is correctly displayed on the screen regardless of the field.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a vertical screen position adjustment circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of a vertical screen position adjustment circuit according to an embodiment of the present invention, and FIG. 3 is a conventional vertical screen position adjustment circuit. FIG. 4, a block diagram of the circuit, is a plan view showing an abnormal screen display when a conventional vertical screen position adjustment circuit is used. 4... Vertical blanking circuit, 6... Field detection circuit, 7... Vertical synchronization signal delay circuit, 8... Vertical deflection circuit. Name of agent: Patent attorney Shigetaka Awano and one other person 'M leap-signal (1 凰ふ-f--１→←--Th
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Claims (1)

[Claims] a field detection circuit that detects whether the vertical synchronization signal is an odd field or an even field and takes different outputs depending on whether the vertical synchronization signal is the odd field or the even field; a vertical synchronizing signal delay circuit which receives the signal and the output of the field detection circuit and delays the vertical synchronizing signal in synchronization with the horizontal synchronizing signal, and the vertical synchronizing signal delay circuit delays the horizontal scanning period during the even field. delaying the vertical synchronizing signal by 1/2 period and applying it to the vertical deflection circuit;
A vertical screen position adjustment circuit characterized in that it outputs a vertical synchronization signal that is temporally earlier than the delayed vertical synchronization signal by one period of the horizontal synchronization signal.