JPH0435408A - Delay circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a switching means which inputs at least more than one delay signals outputted from respective connection points of transfer gates, selects one of the delay signals and outputs it. CONSTITUTION:A signal which is always high is inputted to an invertor 2 and all the transfer gates 4, 5, 6, 7 and 8 come to an on-state. When a signal 101 is inputted to an invertor 1, the delay signals corresponding to the outputs of the transfer gates are outputted from the transfer gates 4, 5, 6, 7 and 8 and they are inputted to the switching circuit 9. When the switching circuit 9 selects the delay signal outputted from the transfer gate 8, the delay signal 102 is outputted from the switching circuit 9 and is inputted to an invertor 10. Then, the desired delay signal 103 is outputted through the shaping operation of the invertor 10. Thus, power consumption can be reduced by using the transfer gates as the delay circuit elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit, and particularly to a delay circuit formed by an LSI logic circuit.

[Conventional technology]

Conventionally, this type of logic circuit utilizes the amount of delay exhibited by a gate circuit as a delay circuit element, and connects a number of gate circuits corresponding to the required amount of delay in series to form Ili. It is common.

FIG. 3 is a circuit diagram of an example of a conventional delay circuit. As shown in Figure 3, as a gate circuit,
Inverter 10. ]1.12, 13.14 and I5 are connected in cascade. For example, the fourth delay circuit
When a waveform as shown in FIG. 4(a) is input, a delayed waveform as shown in FIG. 4(b) is output.

[Problem to be solved by the invention]

The above-described conventional delay circuit is configured by utilizing the amount of delay that the gate circuit itself has and cascading a number of gate circuits corresponding to the required amount of delay. Therefore, since the gate circuit forming the delay circuit acts as an active element, there is a drawback that power consumption increases as the number of delay circuit elements increases.

[Means to solve the problem]

The delay circuit of the present invention is a delay circuit used in an LSI logic circuit, and includes at least one or more transfer gates connected in series as delay circuit elements, and at least one transfer gate output from each connection point of the transfer gates. The apparatus is configured to include a switching means for inputting the above delayed signals and selecting and outputting one of the delayed signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes inverters 1, 2, 3 and 10, transfer gates 4 to 8 consisting of a combination of P-channel MO8) transistors and N-channel MOS F-transistors, and switching The circuit 9 is configured to include a circuit 9.

In FIG. 1, a high signal is constantly input to the inverter 2, and the transfer gates (-4, 5, 6)
, 7 and 8 are all turned on. Figure 2 (a>
, (b) and (C) are the timing charts of the main signals. When the signal 101 shown in the second section (a) is input to the inverter 1, the transfer gate 4.56 Delayed signals corresponding to the respective transfer gate outputs are outputted from .7 and 8, and input to the switching circuit 9. Needless to say, the greater the number of transfer gates that pass, the greater the amount of delay of the delayed signal.

Now, assuming that the delay signal output from the transfer gate 8 is selected in the switching circuit 9, the second
As shown in FIGS. (a) and (b), a delay signal 102 is output from the switching circuit 9 and input to the inverter 10, and through the shaping action of the inverter 10, a desired delay signal 103 is output. Ru.

Therefore, by appropriately switching and outputting the delayed signals outputted from each transfer gate in the switching circuit 9, the inverter 10 selects and outputs the delayed signals corresponding to the desired amount of delay. Furthermore, by using the transfer gate as a delay circuit element, power consumption can be reduced.

〔Effect of the invention〕

As explained in detail above, the present invention uses a transfer gate as a delay circuit element to achieve
This has the advantage that it is possible to provide a delay circuit with low power consumption in an LSI logic circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing chart of main signals in the embodiment, and FIG.
The figure is a circuit diagram of a conventional example. In the figure, 1 to 3, 10 to 16...inverter, 4 to 8...-transfer gate, 9...
...Switching circuit. lθ/yPJl diagram

Claims (1)

[Claims] In delay circuits used in LSI logic circuits,
At least one or more transfer gates connected in series as delay circuit elements and at least one or more delayed signals output from each connection point of the transfer gates are input, and one of the delayed signals is selected. A delay circuit comprising: switching means for outputting the signal.