JPH0466136B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a pulse width modulation circuit in which the number of pulses in one period of a pulse width modulation signal is set by N setting binary signals, and in particular, This invention relates to reducing the number of components of a width modulation circuit.

[Conventional technology]

FIGS. 3 to 8 are circuit diagrams of conventional pulse width modulation circuits, in particular those that receive six set binary signals as input. In the figure, u ₁ to _{u 6} are frequency-divided signals as shown in FIG. ⁸ obtained by frequency ^- dividing the reference pulse signal u ₀ , respectively. These are frequency division signals of frequency division by ³ , frequency division by ²⁴ , frequency division by ²⁵ , and frequency division by ²⁶ .
DAC0 to DAC5 are six set binary signals that specify the number of pulses in one period of the pulse width modulation signal, and these mean 6-bit binary numbers, where DAC0 corresponds to the least significant bit and DAC5 corresponds to the most significant bit. There are things to do.

In FIG. 3, 1a to 1f are CMOS inverters as shown in FIG. 4, to which frequency-divided signals _u1 to _u6 are respectively input. 2a to 2f are CMOS NAND gates as shown in FIG. 5, the NAND gate 2a receives the output signal of the inverter 1a and the setting binary signal DAC5, and the NAND gate 2b receives the output signal of the inverter 1b and the setting binary signal DAC4. The NAND gate _2c receives the output signal of the inverter 1c, the setting binary signal DAC3, and the frequency divided signals u ₁ and u ₂ .
The NAND gate 2d receives the output signal of the inverter 1d, the setting binary signal DAC2, and the divided signal u ₁ ,
u ₂ and u ₃ are inverter 1 in NAND gate 2e.
The output signal of the inverter 1f and the setting binary signal DAC1 and the frequency-divided signals u ₁ , u ₂ , u ₃ , u ₄ are sent to the NAND gate 2f.
DAC0 and frequency-divided signals u ₁ , u ₂ , u ₃ , u ₄ , and u ₅ are input. 3 is this NAND gate 2a
A NOR as shown in Figure 6 where the signal from ~2f is input via CMOS inverter 4a or 4f.
At the gate, the output signal, which is a pulse width modulated signal, is passed from this NOR gate 3 through the CMOS inverter 5.
It outputs PWM.

Next, the operation of the pulse width modulation circuit configured as described above will be explained based on the timing chart shown in FIG.

Now, assuming that the digital value of the six setting binary signals DAC0 to DAC5 is (101010) ₂ = (42) ₁₀ , the setting binary signals are DAC0=“0” and DAC1=
“1”, DAC2="0", DAC3="1", DAC4=
“0” and DAC5=“1”, so the output signals b, d, f of CMOS inverters 4b, 4d, 4f all become “0” level, and the output signal a of CMOS inverter 4a is the frequency-divided signal u ₁ The inverted signal of , the output signal c of the CMOS inverter 4c generates one pulse at the 5th reference pulse number, and hereinafter, the reference pulse number 8
The output signal e of the CMOS inverter 4e generates one pulse at the 17th reference pulse, and thereafter outputs one pulse every 32 reference pulses. It serves as a signal. Therefore, as shown in the figure, from the CMOS inverter 5 which receives these output signals a to f via the NOR gate 3, the number of reference pulses per half cycle is 32, and the number of reference pulses during this half cycle is 21, that is, one cycle. In this case, a pulse width modulation signal (PWM) that is at the "1" level during a period of 42 reference pulses is output.

[Problem that the invention seeks to solve]

In the conventional pulse width modulation circuit, all the gates are configured independently as described above, so for example, when configuring a circuit with four set binary signals,
The number of components required is 54, 92 for 6, 8
138 elements are required for 1, and n ² + 9n + 2 are required for n elements, so the more you try to increase the number of binary signals to improve the function of the pulse width modulation circuit, the more the number of constituent elements will increase in a geometric series. The problem is that a very large number of constituent elements are required.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a pulse width modulation circuit in which the number of constituent elements increases even if the number of set binary signals is increased.

Another object of the present invention is to obtain a pulse width modulation circuit in which power consumption is reduced in addition to the above object.

[Means for solving problems]

In the pulse width modulation circuit according to the present invention, a P-channel MOS transistor is connected between a first power source and an output terminal, an inverted signal of a reference pulse signal is input to the gate, and in the first transistor group, the output terminal is connected to a P-channel MOS transistor. and one end of the transistor, and the second transistor group has N transistors (N is an integer) in which a signal value determination signal for determining the output signal value is input to each gate, and the second transistor group has: One end of the Mth transistor (1≦M≦N: M is an integer) is connected to the other end of the Mth transistor of the first transistor group, and the ^2M portion of the reference pulse signal is connected to the gate of the Mth transistor. The third transistor group has N transistors to which an inverted signal of the frequency signal is input.
1: One end of the transistor (K is an integer) is connected to the other end of the Kth transistor of the second transistor group, and the other end of the Kth transistor is connected to the other end of the K+1th transistor of the second transistor group. It has N-1 transistors that input a ^2K frequency divided signal of the reference pulse signal to the gate of the K-th transistor, and a stabilizing means is connected to the output terminal to maintain the signal from the output terminal at a constant level. This is to stabilize it.

[Effect]

In this invention, N setting transistors, N first frequency dividing transistors, and (N-
1) The number of second frequency dividing transistors are connected in a domino style, and the signal processing for the input signal is performed by this, so the number of elements that increase each time the number of set binary signals increases by one is an arithmetic series. become.

Further, in another aspect of the present invention, the high potential supply element and the low potential supply element are alternately conductive, so that no current passes through between the high potential point and the low potential point.

〔Example〕

FIG. 1 is a circuit diagram of a 6-bit pulse width modulation circuit showing an embodiment of the present invention.
is a reference pulse signal u0 as shown in FIG. 8, six types of divided signals u1 to u6 obtained by frequency-dividing this reference pulse signal u0, and six setting binary signals DAC.
The signal processing section 7 of the domino circuit 6 includes a P channel type MOS high potential supply transistor 9a as a source power source which inputs the reference pulse signal u0 via an inverter 8a. , N-channel MOS setting transistors 13a to 13a whose drains are connected to the drain of the high potential supply transistor 9a, and to which a total of six setting binary signals DAC0 to DAC5 are applied, one to each gate. 13f,
The respective drains are connected to the sources of these setting transistors 13a to 13f, and a total of six types of frequency-divided signals u1 to u6, one type to each gate, are connected to the inverter 11 as shown in FIG.
N-channel MOS first frequency dividing transistor 1 applied as a first frequency divided signal via a and 11f
Six series bodies 24a to 24 consisting of 2a to 12f
f, and these first frequency dividing transistors 12a to 12
The sources of all the first frequency dividing transistors 12a to 12f are interposed between the sources of each of the frequency divided signals u1 to u6 to be applied, that is, the kth and k+1st (1≦k ≦6 (an integer ^of frequency signal directly to the gate
A second frequency dividing transistor 10a to 10e of N-channel MOS is applied as a frequency divided signal, and a second frequency dividing transistor to which a frequency divided signal u1 having the smallest frequency division among the second frequency dividing transistors 10a to 10e is applied. A source-grounded transistor whose drain is connected to the source of the transistor 10a and whose gate receives the reference pulse signal u0 via the inverter 8a.
Channel type MOS low potential supply transistor 9b
The output section 14 is a fourth transistor whose input terminal is connected to the drain of the high potential supply transistor 9a.
Inverter 15 as shown in the figure and this inverter 15
Each gate is connected to the output terminal of
It consists of a P-channel MOS transistor 16 whose source is a power supply and whose drain is connected to the input terminal, and an N-channel MOS transistor 17 whose source is grounded. Reference numeral 18 denotes a D flip-flop bistable circuit which inputs the output signal from the domino circuit 6 and outputs a signal corresponding to the reference pulse signal u0. Inverter 1 as shown
9 and the reference pulse signal u0 as the other input via an inverter 8a, and the AND gate 20 as shown in FIG. At the end, input the output signal of this AND gate 20,
At the other input terminal, two NOR gates 2 as shown in FIG. 5 are connected to input the output signal from the domino circuit 6.
1 and 22, and an inverter 23 that inverts the output signal of the NOR gate 22 and outputs it as a pulse width modulation signal (PWM).

The specific operation of the pulse width modulation circuit configured as described above will now be explained based on the timing chart of FIG. Now for example, set binary signal DAC
Assuming that the digital value from 0 to DAC5 is set to (101010) ₂ = (42) and ₁₀ as before,
The setting binary signal is DAC0="0", DAC1="1",
DAC2="0", DAC3="1", DAC4="0",
Since DAC5="1", setting transistor 1
3a, 13c, and 13e are rendered nonconductive, and setting transistors 13b, 13d, and 13f are rendered conductive.
Therefore, the output signal A at the first output point 24 is "0" when the reference pulse signal u0 and the frequency division signal u1 are "0", or when the reference pulse signal u0 and the frequency division signal _u3 are "0".
And when the frequency division signals u ₁ , u ₂ are “1”, or when the reference pulse signal u 0 and the frequency division signal u ₅ are “0” and the frequency division signals u ₁ , u ₂ , u ₃ , u ₄ are “1” It becomes "0" only when , and "1" at other times. This is inverted via the inverter 15, and then the signal B from the inverter 15 is converted into the reference pulse signal u0 by the bistable circuit 18. A pulse width modulation signal PWM is obtained by delaying the signal by an inverse period.

In the pulse width modulation circuit configured as described above, an output corresponding to the output of the inverter 4a in the conventional circuit is obtained at the drain of the setting transistor 13f, and an output corresponding to the output of the inverter 4b is obtained from the setting transistor 13e. The output of the inverter 4c is obtained at the drain of the setting transistor 13d, the output of the inverter 4d is obtained at the drain of the setting transistor 13c, and the output of the inverter 4e is obtained at the drain of the output setting transistor 13b.
The inverter 4f output is obtained from the drain of the setting transistor 13a, but from the viewpoint of reducing power consumption, the high potential supply transistor 9a and the low potential supply transistor 9a, in which one becomes non-conductive when one is conductive, and the other becomes non-conductive. Since the transistor 9b is provided, the output signal B from the domino circuit 6 is actually
cannot be the same as before. Therefore, in this embodiment, the D flip-flop 18 is connected to the domino circuit 6, and the D flip-flop 18 is connected to the domino circuit 6.
8 with the reference pulse signal u0, the same pulse width modulation signal PWM as the conventional one can be generated for the first time.
By doing so, it is possible to realize a circuit with a small number of elements and a reduction in power consumption.

In the above embodiment, the high potential supply transistor is a P-channel MOS transistor, but it may also be an N-channel MOS transistor. In that case, the reference pulse signal u0 can be directly applied without going through the inverter 8a. For example, as in the above embodiment, power consumption can be reduced and the number of elements can be reduced.

Further, in the above embodiment, the high potential supply transistor 9a, the low potential supply transistor 9b, and the bistable circuit 18 are provided in order to reduce power consumption, but these may be deleted, and in this case, the high potential supply transistor 9a Alternatively, an N-channel MOS transistor with the gate and drain connected to the power supply Vcc, or a gate connected to the grounded source power supply Vcc
It is sufficient to provide a load element such as a P-channel MOS transistor connected to.

Further, in the above embodiment, there are six types of setting binary signals, but the number is not limited to six types, but the setting transistor 13 and the first and second frequency dividing transistors are changed each time the number of setting binary signals increases by one type. 10,
12 and the inverter 11 may be newly provided, and in that case, it is only necessary to increase the number of transistors by five.

〔Effect of the invention〕

As explained above, in this invention, N setting transistors, N first frequency dividing transistors, and N-1 second frequency dividing transistors are connected in a domino style, whereby signal processing for input signals is performed. Since the number of elements increases each time the number of set binary signals increases by one, the number of elements increases only in an arithmetic progression, and the larger the number of set binary signals, the greater the reduction in the number of constituent elements. It has the effect of being able to

Since the drains of a plurality of N-channel MOS setting transistors whose gates are applied with setting binary signals are connected to the drain of a common P-channel MOS high-potential supply transistor, the chip area can be reduced.

Further, another aspect of the present invention is that since the high potential supply element and the low potential supply element are alternately conductive, current does not pass between the high potential point and the low potential point, thereby achieving the above-mentioned effect. In addition to this, it has the effect of further reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Figure 2 is a timing diagram of the circuit in Figure 1, and Figure 3 is a timing diagram of the circuit in Figure 1.
The figure is a circuit diagram of a conventional pulse width modulation circuit, and Figures 4 to 6 are circuit diagrams of the inverter, NAND gate, and NOR gate used in Figures 1 and 3, respectively. , Figure 7 is
FIG. 3 is a timing diagram of the output signal of the circuit, and FIG. 8 is a timing diagram of the reference pulse signal and the frequency division signal. In the figure, 9a is a high potential supply transistor;
9b is a low potential supply transistor, 10 is a second frequency dividing transistor, 12 is a first frequency dividing transistor, 1
3 is a setting transistor, 24 is a series body, u0 is a reference pulse signal, and u1 to u6 are second frequency divided signals. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A P-channel MOS transistor connected between a first power supply and an output terminal, and having an inverted reference pulse signal input to its gate; and one terminal of the transistor connected to the output terminal. N signal value determination signals are input to each gate (N is an integer) to determine the signal value to be output.
one end of the Mth (1≦M≦N: M is an integer) transistor and the other end of the Mth transistor of the first transistor group are connected, and the Mth a second transistor group having N transistors to which an inverted signal of the ^2M frequency-divided signal of the reference pulse signal is input to the gates of the transistors; and a K-th transistor (1≦K≦N-1: K is an integer). one end of the K-th transistor is connected to the other end of the K-th transistor of the second transistor group, the other end of the K-th transistor is connected to the other end of the K+1-th transistor of the second transistor group, and the K-th transistor a third group of N-1 transistors to which a ^2K frequency-divided signal of the reference pulse signal is input to the gate of the transistor; and a stabilizing means connected to the output terminal to stabilize the signal from the output terminal at a constant level. A pulse width modulation circuit characterized by comprising: