JPH04354342A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04354342A
JPH04354342A JP3156133A JP15613391A JPH04354342A JP H04354342 A JPH04354342 A JP H04354342A JP 3156133 A JP3156133 A JP 3156133A JP 15613391 A JP15613391 A JP 15613391A JP H04354342 A JPH04354342 A JP H04354342A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
leads
contact pads
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3156133A
Other languages
Japanese (ja)
Inventor
Naoyuki Sadahira
定平 尚之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP3156133A priority Critical patent/JPH04354342A/en
Publication of JPH04354342A publication Critical patent/JPH04354342A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To stably obtain excellent characteristics of a semiconductor chip by arranging a heat sink on a front and/or rear surface of the chip. CONSTITUTION:A semiconductor device in which a semiconductor chip 2 formed with many contact pads and a wiring sheet in which leads 4 are previously formed on a front surface of an insulation film 3, are so laminated that the leads 4 are superposed on the contact pads of the chip 2 through a bump 5, thermally connected, and sealed with plastic 6, is provided.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、多数の接点パッドを
形成した半導体チップと絶縁フィルムの表面にあらかじ
めリードを形成した配線シートとを、前記リードが半導
体チップの接点パッドにバンプを介して重なるように重
ね合わせて加熱接合し、プラスチックで封止してなる半
導体装置、いわゆるTAB(Tape Automat
ed Bonding)技術で作製したTCP(Tap
e Carrier Packege)に関するもので
ある。
[Industrial Application Field] This invention provides a method for connecting a semiconductor chip on which a large number of contact pads are formed and a wiring sheet on which leads are previously formed on the surface of an insulating film so that the leads overlap the contact pads of the semiconductor chip via bumps. The so-called TAB (Tape Automated
TCP (Tap
e Carrier Package).

【0002】0002

【従来の技術】TABは、有機絶縁フィルム(例えばポ
リイミド製)にCu箔を張り、このCu箔をエッチング
して配線パターン(リード)を形成したテープ(TAB
テープ)を準備し、このTABテープのリードを、バン
プを介して半導体チップの接点パッドに重ね合わせ加熱
接合して半導体チップを実装する技術である。このTA
Bは、従来用いられてきたワイヤーボンディングに比べ
て、■半導体チップに形成する接点パッド及びそのピッ
チを狭くできるので、接点パッドの数を数多くとること
ができる。■ワイヤーを引き回すことがないので、実装
に必要な空間を薄くすることができる。■リード・パタ
ーンの形状は制約がないので、自由に変えることができ
る。■折り曲げることができる。■複数個の接点パッド
とリードとを、同時に接合することができるので、接合
時間を短縮することができる。等の特徴を有しているた
め、近年の高密度化、多ピン化、薄型化の要請に有利に
適合する、有望な技術と言える。
[Prior Art] TAB is a tape (TAB) in which a Cu foil is applied to an organic insulating film (for example, made of polyimide) and a wiring pattern (lead) is formed by etching the Cu foil.
This is a technique in which a semiconductor chip is mounted by preparing a TAB tape (TAB tape), overlapping the leads of this TAB tape with the contact pads of a semiconductor chip via bumps, and bonding them by heating. This TA
Compared with the conventionally used wire bonding method, (1) the contact pads formed on the semiconductor chip and the pitch thereof can be narrowed, so a large number of contact pads can be provided. ■Since there is no need to route wires, the space required for mounting can be reduced. ■There are no restrictions on the shape of the lead pattern, so it can be changed freely. ■Can be bent. - Since multiple contact pads and leads can be bonded at the same time, bonding time can be shortened. Because it has the following characteristics, it can be said to be a promising technology that advantageously meets the recent demands for higher density, higher pin count, and lower thickness.

【0003】TCPは、このようなTAB技術によって
半導体チップとリードとを電気的に接続した後、プラス
チックで封止することで得られている。
[0003] TCP is obtained by electrically connecting a semiconductor chip and leads using the TAB technique, and then sealing the semiconductor chip with plastic.

【0004】しかしながら、かかるTCPは、多ピン化
すなわち半導体チップの高集積度化に伴って半導体チッ
プからの発熱量が増大する傾向にあるにもかかわらず、
TABテープやモールド用樹脂の熱伝導性が良好とは言
い難いため、半導体チップの放熱性の点で問題があり、
半導体チップが良好な特性を安定して得るために問題で
あった。この問題は通常用いられる、いわゆるリードフ
レームとワイヤボンディング法とを用いて作製される半
導体装置と比べても、ダイパッドがない分、放熱性が悪
くなっていて、問題であった。
However, in such TCPs, the amount of heat generated from the semiconductor chip tends to increase as the number of pins increases, that is, the degree of integration of the semiconductor chip increases.
Since the thermal conductivity of TAB tape and molding resin is not good, there are problems with the heat dissipation of semiconductor chips.
This has been a problem for semiconductor chips to stably obtain good characteristics. This problem has been a problem since the lack of a die pad results in poor heat dissipation compared to a semiconductor device manufactured using a commonly used so-called lead frame and wire bonding method.

【0005】上述のTCPの放熱問題に対して、パッケ
ージに放熱フィンを突設することが考えられたが、かか
る放熱フィンを突設することは、TCPの特徴である薄
型化というメリットを失ってしまう問題があり、またコ
ストも増大させてしまうという問題もあった。
[0005] In order to solve the above-mentioned TCP heat dissipation problem, it has been considered to provide heat dissipation fins protruding from the package, but providing such protruding heat dissipation fins loses the advantage of thinning, which is a characteristic of TCP. There is also the problem of increasing the cost.

【0006】この他、半導体チップをリードフレームの
ダイパッドにダイボンディングした半導体装置において
は、放熱フィンを、リードフレームに沿って配設した構
造のデバイスや、封止材のクラックの伝播を防止するた
めにダイパッドの裏面の封止材をあらかじめ解放した構
造のデバイスがあるが、これらの半導体装置はいずれも
ワイヤーボンディングを行うために、ワイヤーの引き回
しの制約から薄型化が困難であるばかりでなく、前者は
、アウターリード数は放熱フィンの占有分だけ減少する
ことになって多ピン化に不適合であり、また後者は、T
CPにはダイパッドがないために適用できない。
In addition, in semiconductor devices in which a semiconductor chip is die-bonded to a die pad of a lead frame, heat dissipation fins are used to prevent propagation of cracks in the encapsulant and devices that are arranged along the lead frame. There are devices in which the encapsulant on the back side of the die pad is released in advance, but since all of these semiconductor devices use wire bonding, it is not only difficult to make them thinner due to restrictions on wire routing. In the latter case, the number of outer leads decreases by the amount occupied by the radiation fins, making it unsuitable for increasing the number of pins.
This cannot be applied to CP because it does not have a die pad.

【0007】[0007]

【発明が解決しようとする課題】上述したTCPの放熱
問題を有利に解決し、TCPの半導体チップが良好な特
性を安定して得ることのできる半導体装置を提案するこ
とがこの発明の目的である。
[Problems to be Solved by the Invention] It is an object of the present invention to propose a semiconductor device that advantageously solves the above-mentioned TCP heat dissipation problem and allows a TCP semiconductor chip to stably obtain good characteristics. .

【0008】[0008]

【課題を解決するための手段】この発明は、多数の接点
パッドを形成した半導体チップと絶縁フィルムの表面に
あらかじめリードを形成した配線シートとを、前記リー
ドが半導体チップの接点パッドにバンプを介して重なる
ように重ね合わせて加熱接合し、プラスチックで封止し
てなる半導体装置において、上記半導体チップの少なく
とも片面に、放熱板を配設したことを特徴とする半導体
装置である。
[Means for Solving the Problems] The present invention connects a semiconductor chip on which a large number of contact pads are formed and a wiring sheet on which leads are formed in advance on the surface of an insulating film, and the leads are connected to the contact pads of the semiconductor chip via bumps. The present invention is a semiconductor device formed by stacking the semiconductor chip overlappingly, thermally bonding it, and sealing it with plastic, characterized in that a heat sink is disposed on at least one side of the semiconductor chip.

【0009】[0009]

【作用】この発明の半導体装置は、半導体チップの表面
及び/又は背面に放熱板を配設することから、プラスチ
ックでパッケージした半導体装置の熱容量を下げる他、
放熱効率が向上するのでTCPの半導体チップの良好な
特性を安定かつ低コストに得ることが可能となる。
[Function] The semiconductor device of the present invention has a heat dissipation plate on the front and/or back side of the semiconductor chip, which reduces the heat capacity of the semiconductor device packaged with plastic.
Since the heat dissipation efficiency is improved, it becomes possible to stably obtain good characteristics of the TCP semiconductor chip at low cost.

【0010】0010

【実施例】以下図面を用いてこの発明の半導体装置を具
体的に説明する。図1は、この発明の半導体装置の一例
を示す断面図である。かかる半導体装置1は、半導体チ
ップ2と、TABテープ3上に形成したCuリード4と
を、バンプ5を介して加熱接合して、電気的に接合する
ように構成し、かつこれらをプラスチックパッケージ6
により封止している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be specifically explained below with reference to the drawings. FIG. 1 is a sectional view showing an example of a semiconductor device of the present invention. This semiconductor device 1 is configured such that a semiconductor chip 2 and a Cu lead 4 formed on a TAB tape 3 are thermally bonded via bumps 5 to electrically bond them, and these are bonded together in a plastic package 6.
It is sealed by.

【0011】この発明では、かかる半導体装置1内部の
半導体チップ2に、放熱板7を配設したことが特徴であ
る。このように半導体装置1内部の半導体チップ2に、
放熱板7を配設することによって、パッケージの薄型化
というTCPのメリットを失うことなく、また比較的少
ないコストで、パッケージの熱容量を十分に下げること
ができるので、放熱板7がプラスチックパッケージ6内
に埋め込まれている図1の例でも半導体チップ2の放熱
は十分満足できる。これに対して図2に示すように、パ
ッケージ6に放熱フィン8を突設した従来の半導体装置
では、TCPの特徴である薄型化というメリットを失っ
てしまう問題があり、またコストも増大させてしまうの
は前述したとおりである。
The present invention is characterized in that a heat sink 7 is disposed on the semiconductor chip 2 inside the semiconductor device 1. In this way, in the semiconductor chip 2 inside the semiconductor device 1,
By providing the heat sink 7, the heat capacity of the package can be sufficiently lowered without losing the TCP advantage of making the package thinner and at a relatively low cost. Even in the example of FIG. 1 in which the semiconductor chip 2 is embedded in the semiconductor chip 2, the heat dissipation of the semiconductor chip 2 is sufficiently satisfactory. On the other hand, as shown in FIG. 2, in the conventional semiconductor device in which the heat dissipation fins 8 are provided protruding from the package 6, there is a problem that the advantage of thinning, which is a characteristic of TCP, is lost, and the cost also increases. As mentioned above, it is put away.

【0012】図3に、この発明の他の実施例を断面で示
す。同図では、放熱板7の厚みを、プラスチックパッケ
ージの表面と面一になるように選択した例である。この
例では、放熱板7がプラスチックパッケージの表面に面
一で露出していることから、TCPの薄型化を維持した
ままで放熱効率がさらに向上する。
FIG. 3 shows another embodiment of the invention in cross section. The figure shows an example in which the thickness of the heat sink 7 is selected so that it is flush with the surface of the plastic package. In this example, since the heat dissipation plate 7 is exposed flush with the surface of the plastic package, the heat dissipation efficiency is further improved while maintaining the thinness of the TCP.

【0013】図1及び図3に示したように放熱板7は、
TCPの利点である薄型化を損ねないために、プラスチ
ックパッケージ6から突出しないようにする。したがっ
て放熱板7の厚みは、プラスチックパッケージ6の厚み
にもよるが、0.1 〜0.5 mm程度とすることが
好ましい。
As shown in FIGS. 1 and 3, the heat sink 7 is
It should not protrude from the plastic package 6 so as not to impair the thinness that is an advantage of TCP. Therefore, the thickness of the heat sink 7 is preferably about 0.1 to 0.5 mm, although it depends on the thickness of the plastic package 6.

【0014】図4にこの発明の他の実施例を断面で示す
。同図では、放熱板7及び9を、半導体チップの表面に
配設(放熱板7)しかつ背面にも配設(放熱板9)した
例である。このように放熱板を、半導体チップの表面及
び背面のいずれにも配設することによって、半導体チッ
プの放熱効率はさらに向上するのである。
FIG. 4 shows a cross-sectional view of another embodiment of the present invention. The figure shows an example in which heat sinks 7 and 9 are provided on the front surface of the semiconductor chip (heat sink 7) and also on the back surface (heat sink 9). By disposing the heat sink on both the front and back surfaces of the semiconductor chip in this manner, the heat radiation efficiency of the semiconductor chip is further improved.

【0015】放熱板の配設は、半導体チップの組立て工
程、なかでもインナーリードボンディングの前、後に、
放熱板例えば銅板、アルミニウム板等の金属板を半導体
チップの表面及び/又は背面に熱伝導性接着剤等を用い
て貼付すればよい。図1及び図3に示すように、放熱板
を半導体チップの表面に貼付する場合には、電気絶縁性
の接着剤を用いることがチップの信頼性の観点から好ま
しい。かかる接着剤としては、シリコン樹脂等が挙げら
れる。
[0015] The heat sink is disposed during the semiconductor chip assembly process, especially before and after inner lead bonding.
A heat sink, such as a metal plate such as a copper plate or an aluminum plate, may be attached to the front and/or back surface of the semiconductor chip using a thermally conductive adhesive or the like. As shown in FIGS. 1 and 3, when attaching a heat sink to the surface of a semiconductor chip, it is preferable to use an electrically insulating adhesive from the viewpoint of reliability of the chip. Such adhesives include silicone resins and the like.

【0016】この発明は上述した実施例に限られること
はなく、例えば放熱板を半導体チップの裏面のみに配設
しても良いことは言うまでもない。
It goes without saying that the present invention is not limited to the embodiments described above, and that the heat sink may be provided only on the back surface of the semiconductor chip, for example.

【0017】[0017]

【発明の効果】この発明の半導体装置は、半導体チップ
の表面及び/又は背面に放熱板を配設することから、T
CPの半導体チップの良好な特性を安定かつ低コストに
得ることができる。
Effects of the Invention The semiconductor device of the present invention has a heat dissipation plate on the front surface and/or back surface of the semiconductor chip, so that T
Good characteristics of a CP semiconductor chip can be obtained stably and at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】図1は、この発明の半導体装置の一例を示す断
面図である。
FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention.

【図2】図2は、従来の半導体装置を示す断面図である
。
FIG. 2 is a cross-sectional view showing a conventional semiconductor device.

【図3】図3は、この発明の半導体装置の他の例を示す
断面図である。
FIG. 3 is a cross-sectional view showing another example of the semiconductor device of the present invention.

【図4】図4は、この発明の半導体装置の他の例を示す
断面図である。
FIG. 4 is a cross-sectional view showing another example of the semiconductor device of the invention.

【符号の説明】[Explanation of symbols]

1  半導体装置 2  半導体チップ 3  TABテープ 4  Cuリード 5  バンプ 6  プラスチックパッケージ 7  放熱板 1 Semiconductor device 2 Semiconductor chip 3 TAB tape 4 Cu lead 5 Bump 6 Plastic package 7 Heat sink

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  多数の接点パッドを形成した半導体チ
ップと絶縁フィルムの表面にあらかじめリードを形成し
た配線シートとを、前記リードが半導体チップの接点パ
ッドにバンプを介して重なるように重ね合わせて加熱接
合し、プラスチックで封止してなる半導体装置において
、上記半導体チップの表面及び/又は背面に、放熱板を
配設したことを特徴とする半導体装置。
1. A semiconductor chip on which a large number of contact pads are formed and a wiring sheet on which leads are previously formed on the surface of an insulating film are placed one on top of the other and heated so that the leads overlap the contact pads of the semiconductor chip via bumps. 1. A semiconductor device formed by bonding and sealing with plastic, characterized in that a heat sink is disposed on the front surface and/or back surface of the semiconductor chip.
JP3156133A 1991-05-31 1991-05-31 Semiconductor device Pending JPH04354342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3156133A JPH04354342A (en) 1991-05-31 1991-05-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3156133A JPH04354342A (en) 1991-05-31 1991-05-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04354342A true JPH04354342A (en) 1992-12-08

Family

ID=15621048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3156133A Pending JPH04354342A (en) 1991-05-31 1991-05-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04354342A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321252A (en) * 1994-05-19 1995-12-08 Nec Corp Resin-sealed semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270335A (en) * 1988-04-22 1989-10-27 Hitachi Ltd Semiconductor device
JPH02306654A (en) * 1989-05-20 1990-12-20 Hitachi Ltd Semiconductor device and electronic device using same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270335A (en) * 1988-04-22 1989-10-27 Hitachi Ltd Semiconductor device
JPH02306654A (en) * 1989-05-20 1990-12-20 Hitachi Ltd Semiconductor device and electronic device using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321252A (en) * 1994-05-19 1995-12-08 Nec Corp Resin-sealed semiconductor device

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