JPH0435965A - Printing head controller - Google Patents

Abstract

PURPOSE:To correct the inclination of a pin arrangement of a printing head by providing first and second shift registers using first and second timing signals in synchronism with the rising and falling timing of a conduction time to a printing head as shift clocks and set/reset latch parts for generating printing timing signals for all pins. CONSTITUTION:First and second timers 5, 6 generate first and second timing signals in synchronism with the rising and falling timings of a printing head conduction time with a cycle of a time difference between drive signals for every adjacent pins for correcting the inclination of a pin arrangement of a printing head orthogonal to the travel direction of a carriage. First and second shift registers 10, 11 use the first and second timing signals as shift clocks. Set/rest latch parts 13, 14 generate printing timing signals for all pins using the outputs of the first and second shift registers 10, 11 as set signals. In this construction, a conduction time to a printing head can be maintained without increasing the frequency of a shift clock, and the inclination of the pin arrangement of the printing head can be corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a print head control device for a dot matrix printer.

Conventional technology In recent years, in dot matrix printers, dot matrix printers have been mounted on carriages to avoid noise caused by each pin hitting the dot at the same time, magnetic interference when using a large capacity power supply or electromagnetic force, and for high-density packaging. , a distributed print head is used that prints by supplying a drive signal corresponding to each pin in a row of pins of the print head, the pins of which are arranged at an angle with respect to the direction perpendicular to the direction of movement of the carriage. printhead controllers are used.

A conventional print head control device will be described below.

FIG. 8(a) shows the pin row pattern of a conventional 24-pin wire dot head. Figure 8(b) shows the pin row pattern of a distributed print head in which the pins are arranged at an angle.
C) is another example of a pin array pattern for a distributed print head.

FIG. 9 is a drive timing chart of the 24-pin wire dot head, and FIGS. 9(a), 9(b), and 9(c) are respectively shown in FIGS. ), corresponds to the head with the pin row pattern shown in FIG. 8(C). In the pin row pattern of Fig. 8(a), Fig. 9(a)
As shown in Fig. 8(b), only a timer is required to generate timing T7 which determines the spacing between dots constituting a character, and timing T8 which determines the length Nn of the head coil that drives the pins of the head. ), the drive timing is different for each pin as shown in Figure 9(b), so not only the timer that generates timing T7 and timing T8 but also the delay for each pin according to the slope of the pin arrangement. A timer is required to generate the timing T9 that determines the time, and it is necessary to delay all the drive timings of the 24 pins by the timing T9. Figure 8 (C)
In the pin arrangement shown in FIG. 9(C), the drive timing is delayed for each group of six pins to simplify the control circuit.

, FIG. 10 is a block diagram of a conventional print head control device having the pin arrangement shown in FIG. 8(b). In FIG. 10, 27 is a character font read-only memory (hereinafter referred to as character font RO) in which character font data is written.
It is abbreviated as M. ), 28 is a distribution timing generation unit that generates timing for distributing print data; FIG. 9 (1))
A timer 29 that generates a clock having a timing of T7 and T8, a timer 30 that generates a clock having a timing of T9 as shown in FIG.
．． It consists of an oscillator 31 that operates 30. 32 is a shift register section that delays print data read from the character font ROM 27. 33 is a central processing unit (hereinafter abbreviated as CPU) and a character font ROλ
(27, each of the distributed timing generation section 28 and the shift register section 32 is an input/output section (hereinafter abbreviated as I10 section).

) 34. Reference numeral 35 indicates 24 AND circuits, each of which performs an AND operation between the print data for 24 pins from the CPU 33 and the output of the timer 29. 36 is a head driver that applies a pulse signal to the head coil 37.

The operation of the print head control device configured as described above will be described below.

The CPU 33 uses the timer 29 to generate the timing signal of the first pin (hereinafter abbreviated as shift data) shown in FIG. 9(b).
The falling timing W of is always notified, and the CPU 33
reads the print data for 24 pins from the character font ROM 27 and sends it to the AND circuit 35 according to the timing of the falling edge of the shift data, and the AND circuit 35 outputs each of the print data for the 24 pins and the AN of the output of the timer 29.
D is taken and sent to the shift register section 32. Also timer 30
Then, the character mode data X is received from the CPU 33, and a clock (hereinafter abbreviated as shift clock) having a timing having a period of T9 in FIG. 9 (1) according to the printing mode is sent to the shift register section 32. send to The shift register section 32 generates drive signals for pins 1 to 24 in FIG. 9(b) based on the output signal from the AND circuit 35 and the shift clock, and sends them to the head driver 36. The head driver 36 drives the head by applying a pulse voltage to the head coil 37 using the drive signal 18 from the shift register section 32 . The frequency of the shift clock t changes depending on the printing mode for various characters, but in order to maintain the timing of T8, T8 must be an integral multiple of the shift clock t, so it is inevitable that the frequency of the shift clock t will change. It becomes necessary to increase the frequency, that is, to provide the shift register section 32 with a shift clock obtained by subdividing the T9 period. For this reason, the shift register section 32 has multiple stages of shift registers.

Problems to be Solved by the Invention However, in the conventional configuration, the character phono)ROλ
(The print data read from 27 is reflected in the head coil 24.
The data of the energization time is added to this print data, and the data of the energization time is added to the print data fraction part 3.
The shift register composing the head coil 24 generates distributed data corresponding to each pin in the pin row of the distributed print head, so that the communication between the head coils 24 and 3 can be maintained for all printing modes. It is necessary to increase the frequency of the shift clock so that the energization time of the head coil 240 is always an integral multiple of the period of the shift clock that drives the shift register of the print data distribution section 32. The number of gates increases. In order to reduce the number of gates, a pin array pattern configuration as shown in Figure 8(c) can be used to reduce printing noise and reduce the number of gates.
The effects of power supply capacity reduction, etc. are drastically reduced.

Means for Solving the Problems In order to solve the above problems, the present invention corrects the inclination of the pin rows of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. A first timer that generates a first timer No. 8 synchronized with the rising timing of the print head energization time with a period equal to the time difference between the drive signals for each pin, and a drive signal for each adjacent pin that corrects the inclination of the pin row. a second timer that generates a second timing signal whose period is the time difference between a second shift register that uses the timing signal as a shift clock, and a set/reset latch that uses the output of the first shift register as a set signal and the output of the second shift register as a reset signal to generate print timing signals for all pins. Equipped with a department.

Effect of the Invention With the above-described configuration, the present invention can maintain the energization time of the print head without increasing the frequency of the shift clock, and can correct the inclination of the pin array of the print head that is inclined with respect to the moving direction of the carriage.

Embodiment FIG. 1 is a block diagram of a print head control device in an embodiment of the present invention.

In Fig. 1, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is an input/output unit (hereinafter abbreviated as I10 unit) that serves as an interface between each device, and 3 is a memory only for reading character fonts. (hereinafter abbreviated as character font ROM).

4 is an oscillator, and 5.6.7 is driven by the basic clock a generated by the oscillator 4, and print mode data bl, b2 . b
3 as the start of counting, the inter-dot delay timing signal cl,
c2. This is a timer that outputs c3. 8.9 is timer 5
Print mode data b4. which switches the quality of characters from the CPU 1 using the output c1 of the CPU 1 as a clock. This is a counter that determines the head energization time and print interval time with b5 as the count value. 10 is a shift register that operates using the output dl of the counter 8 as shift data and the output c1 of the timer 5 as a shift clock; 11 is the output d1 of the counter 8
12 is a shift register that operates using the output d2 of the counter 9 as shift data and the output c2 of the timer 7 as a shift clock. A 12-piece reset latch section (hereinafter abbreviated as S-R latch section) 14 operates with the output el as the cell 81a and the output e2 of the shift register 11 as a reset signal to generate timing 1H g for all pins.
is an S-R latch section that generates a timing signal f for all pins using the output e1 of the shift register 10 as a set signal and the output e3 of the shift register 12 as a reset signal, and drives one pin of this timing signal f. The signal f1 to be
Used as an interrupt signal to PU1. The above is the distributed timing generation section 38.

15 and 16, the print data hO from the CPU 1 is set to 1 by the timing signal output f1 of the S-R latch unit 14, respectively.
A latch section 17, which is composed of a flip-flop, outputs data h1 delayed by one data period corresponding to a dot row, and data h2 delayed by one data period from data h1. Select signal i from CPU1
A latch section 18 is composed of a flip-flop that uses the output j of the data selector 17 as input data and uses the output g of the S-R latch section 13 of the distributed timing generation section 38 as a latch clock.
19 is A for ANDing the output g of the S-R latch section 13 and the output of the latch section 18, and outputting the head drive signal m.
It is an ND circuit. The above is the print data synthesis section 39.

A head driver 20 drives the head 19 using the output f of the S-R latch section 14 and the output m of the AND circuit.

FIG. 2(a) is a circuit diagram for one pin of the head driver 20, and FIG. 2(b) is a circuit diagram for driving the head driver 20 (f,
This is the timing chart for the issue. In FIG. 2(a), transistors 22 and 23 are provided at both ends of the head coil 21,
and a diode 24 are connected, and the transistor 2
The emitter of transistor 2 is connected to a power supply, and the emitter of transistor 2 is connected to the collector of transistor 26 through a resistor 25. The emitter of transistor 23 is grounded.

The operation of the print head control device configured as described above will be explained below.

FIG. 3 shows a pattern of pin rows of a head controlled by the print head control device of the present invention. In Figure 3, the pin row pattern of the head is such that among the 24 pins, the odd numbered pins are in the first row and the even numbered pins are in the second row. Of these, pin N and pin (N+2) are shifted by 1/120*1/12 inch in the printing line direction. Here, 17120 inches is the dot spacing between characters. In the following explanation, pin N and pin (N+1) in the first and second columns are driven at the same timing. That is, the interval between the first column and the second column in the print line direction is an integral multiple of 1/120 inch. Furthermore, in order to facilitate control of the 12 pins in the same column, the lower 8 pins are designated as an L block, and the upper 4 pins are designated as an H block.

Figure 4 Ca) shows the output of the distributed timing generator (fi number g
FIG. 4(b) is a timing chart showing the timing for 24 pins of the output signal f of the distributed timing generator. T1 is the basic cycle for printing one dot, T2 is the ON time of the transistor 22 in FIG. 3(a), T3 is the ON time of the transistor 23 in FIG. 3(a), and T5 is the delay time for each pin. The distributed timing generation unit generates a total of 24 basic cycle fg numbers corresponding to each pin and each transistor.

FIG. 5 is a timing chart showing the timing of the distributed timing generator. Qima 5 is a signal c with a period of Tl/12=75 with respect to the print interval Tl of the head.
Generate 1. The counter 8 counts this signal c1 by 12 times, and the high level period T4 is T4=n*T5 (where n is an integer less than 12) and (T2-T5)<T4<T2. The 12-bit shift register 10 operates with dl as shift data and cl as a shift clock, and outputs 12-bit timing signals from output el-1 to el-12. At these outputs, el- el-(n+1) for n (where n=1.2
．． 3. ...11) is number 18, delayed by 15 hours. Here, this 12-bit timing signal is T4=n*T5 (where n is an integer), but since 20T5 changes depending on the character mode, it is not always n*75=T2, so T4=72 Therefore, the timing of T2 in FIG. 4(a) cannot be maintained, and only the rising timing of the head drive timing signal is maintained. Timer 6 is the output C of timer 5
A signal C2 having the same period as 01 and delayed by 16 hours from 01 is output.

Here, T6 is T6+T5*n=T2 (however, n=1.2, 3...
11) It's time to become. 12 pit shift register 1
1 operates using the output d1 of the counter 8 as shift data and the output C2 of the timer 6 as a shift clock, and outputs e2.
Outputs 12-pit timing signals from -1 to e2-12. These outputs have only the falling timing of the timing signal of the head shown in FIG. 4(a). The S-R latch unit 13 uses the rising timing of el-n as the set timing, the falling timing of e2-n as the reset timing, and sets the printing interval time T.
1 and g-1 to g-12 having head energization time T2
The distributed timing signal of 12 pits up to
Obtain the 12-bit signal of a).

The distributed timing signal g explained above is m in FIG. 2(b).
signal (g signal with head print data added)
However, the print head 21 receives the second g signal separately from the g signal.
The drive signal f in Figure (b) is required. This drive signal f is similar to the generation of No. 18 of g, and the timer 7 outputs a signal C3 having the same period as the output C1 of the timer 5 and delayed by 710 hours from 01. Here, TIO is the time T10=T3-T5*n (where n is an integer). The 12-pit shift register 12 has a counter 9
The output d2 of the timer 7 is used as shift data, the output C3 of the timer 7 is used as a shift clock, and the outputs e3-1 to e3-
Outputs a 12-pit timing signal with 12 points. These outputs have only the fall timing of the timing signal of the head shown in FIG. 4(b). The S-R latch unit 14 uses the rising timing of el-n as the set timing, and the falling timing of e3-n as the reset timing, from f-1 to f-12, which guarantees the same print interval T1 and head energization time T3. Dispersion timing No. 18 of all 12 pits, that is, 12 in Fig. 4(b)
Get pit signal.

The above explanation has been given for the print mode of 1/120 inch dot pitch, but for example, when the print mode is 17240 inch dot pitch, T5=T1/6, and T6, Tl01T4, and T3 also change accordingly. Timer 5.
6.7, counter 8.9 receives setting signal b from CPU1.
1, b2, b3, b4, b5, T5, T6. Tl0
1 Determine T4 and T3.

FIG. 6 is a timing chart of the print data synthesis section 39. For example, the print mode has a print dot spacing of 1736.
There is a 0 inch one, but the dot pattern interval of the head is 1/120 inch, so the dispersion timing to divide 1/120 inch into 12 is the 3-dimensional print data hO from CPU 1 with a print dot interval of 1/360 inch. It spans one minute. In order to support these printing modes, first, data ho is assigned hl, h2 . Data delayed by 1 data period and 2 data periods, respectively, are input to the f4t data selector 17, and data j selected by the select signal i from the CPU 1 is obtained.

In the case of Fig. 6, pins 1 to 8, pins 9 to 16, pins 17 to
Each of the 24 print data corresponds to ho, hl, and h2. If the print data interval is fixed at 17120 inches, this data selector 17 and latch section 15
．． 16 is not necessary. As the output of the data selector 17, the print data of each of the 24 pins input to the latch section 18 is latched by the distributed timing signal g shown in FIG. Further, the 24-bit latched data of each pin is ANDed with the distributed timing signal g in an AND circuit 19 to obtain a head drive signal m.

The head driver 20 uses these driving signals m and f.
First, as shown in Figure 2, both m and f are h i
When set to gh, transistors 22 and 23 are turned on, and current 2 flows through the head coil 21 and rises according to the time constant. Next, when m is set to low, 22 is turned off and current flows from the diode 24 to the head coil 21. Next, when f is set to low, the current becomes zero at f♀. Wire dot printers driven by electromagnetic force have a two-stage drive in which both ends of the head coil are switched in order to drive the wire at high speed and with low power consumption. m,
It is driven by head drive signals with f2 types of timing.

The present invention requires only 2000 gates, whereas the conventional circuit requires about 7000 gates. FIG. 7 shows the effect of distributed printing on noise using the circuit of the present invention. It has a noise reduction effect of 7 dB at 1/4 dispersion and 10 dB at 1/12 minute.

Effects of the Invention As described above, the present invention corrects the inclination of the row of pins of the print head mounted on the carriage and inclined with respect to the direction perpendicular to the moving direction of the carriage. The period is the time difference between the first timer that generates the first timing signal synchronized with the rising timing of the print head energization time and the drive signal for each adjacent pin that corrects the inclination of the pin row. a second timer that generates a second timing signal synchronized with the fall timing of the energization time; a first shift register that uses the first timing signal as a shift clock; and a second timing chart that uses the second timing chart as a shift clock. By providing a second shift register with a second shift register and a set/reset latch section that generates print timing signals for all pins by using the output of the first shift register as a set signal and the output of the second shift register as a reset signal, It is possible to maintain the energization time of the print head without increasing the frequency of the shift clock, and to correct the inclination of the pin row of the print head that is inclined with respect to the carriage movement direction, making it possible to reduce the number of gates. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a print head control device according to an embodiment of the present invention, FIG. 2(a) is a circuit diagram for one pin of the head driver 20, and FIG. )) is head driver 2
FIG. 3 is a pattern diagram of the pin array of the head controlled by the print head control device of the present invention, and FIG. 4(b) is a timing chart showing the timing for 24 pins of the output signal f of the distributed timing generator 38. FIG. 5 is a timing chart of the distributed timing generator 38. The figure shows a timing chart of the print data synthesis section 39.
The figure is a block diagram of a conventional print head control device. 0.11.12...Shift register 3.14...S-R latch section 5.16...Latch section 7...Data selector 8...Latch section 19...AND circuit 0...
・Head driver bat...Head coil 2.23...Transistor 4...Diode 25...Resistor 6...Transistor 8...Dispersion timing generation section 9...Print data synthesis section agent Name Patent Attorney Shigetaka Awano One Idiot ■... Central processing unit 2..., Input/output section 3... Character font read-only memory 4... Transmitter 5, 6. 7...Timer 8.9...Counter (a) Figure (b) Figure (a) Figure 4 (b) Pin 9.10 Pin N, +2 Pin +3. +4 Pin 15.16 Pin 17.18 Pin 19.20 Pin 2L22 Pin 23.24 111 "-1111 C-"-111] -1111 Pin 11.12 Pin +3.14 Pin +5. +6 Pin 23.24 Figure 7 Figure 6 Figure 1.2 pin 3.4 pin 5.6 pin 7.8 pin 9.10 pin 11.12 pin 13.14 pin 15.16 pin 17.18 pin 19. 20 pins 21. 22 pins 23. 24 pins Coco T-[]= U'=Zuni-[-]-1'-1'-Coll Figure 8 (a) (b) Frequency 1! (Hzl ( C)

Claims (2)

[Claims] (1) A print head control device mounted on a carriage that performs printing by supplying drive signals corresponding to each pin in a row of pins of the print head that is inclined with respect to the direction perpendicular to the direction of movement of the carriage. a first timing signal that generates a first timing signal synchronized with the rising timing of the energization time of the print head, the period of which is a time difference between drive signals for each adjacent pin that corrects the inclination of the pin row;
and a second timer that generates a second timing signal synchronized with the fall timing of the energization time of the print head, the period of which is the time difference between drive signals for each adjacent pin that corrects the inclination of the pin row. a first shift register using the first timing signal as a shift clock; a second shift register using the second timing signal as a shift clock; and an output of the first shift register as a set signal; A print head control device comprising: a set/reset latch section that operates using the output of the second shift register as a reset signal and generates print timing signals for all pins. (2) The period of the first timer and the second timer changes in response to changes in a plurality of fonts or the number of characters per unit length. print head control device.