JPH0482758A - impact dot printer - Google Patents

Abstract

PURPOSE:To obtain noise reducing effect by extending the driving time interval for pins even when the number of pins to be driven simultaneously increases in a high grade mode. CONSTITUTION:Generally, noise reducing effect is the higher when the fewer the number N of pins which are driven simultaneously is, and the longer between dots delay time T is. In a draft mode with a printing pitch of 1/120 inch, simultaneous driving of N=2 is inevitably generated, and in a NLQ mode with a printing pitch of 1/369 inch, simultaneous driving of N=6 is inevitably generated, and the noise reducing effect for the NLQ mode is lower than that of the draft mode. So, in the NLQ mode, the between dots delay time T is changed without changing N. That is, by a distribution timing ROM 7, for which distribution timing is written, corresponding with 2 types of character fonts for a printer such as draft and NLQ(Near Letter Quality), the number of letters per inch and the printing direction of a head respectively, distribution timing is read to perform printing using output (e) of an address counter 5 and printing mode data (h) to switch over grade of letters from a CPU 1 as address.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an impact dot printer in which an impact print head having a plurality of pins is mounted on a carriage and printing is performed by appropriately driving the pins while moving the carriage. Amo [Prior art] Kinki To reduce noise caused by each dot hitting the dots at the same time in a wired dot matrix printer. Printing by supplying a drive signal according to each pin of a print head in which the pin rows are arranged at an angle. Even if a distributed print head is used that performs the
) and high quality mode with a printing pitch of 1/360 inch (N
Distributed printing of a conventional 24-bin wire dot matrix printer will be explained below using the case of LQ mode) as an example. The draft and NLQ character fonts are usually different character fonts. Even though NLQ has three times as much data as draft in the printing direction, Figure 10(a) shows the relationship between draft and NLQ printing pitch.

Figure 10(b) is a diagram showing the wire arrangement of the dispersion head, in which the 24-dot heads are arranged in two rows in groups of 12 dots each, and each dot row is arranged in the printing direction to correct the printing inclination. Even if it is tilted against the first
FIG. 10(c) is a timing chart showing the head control timing when printing in the draft mode with the head shown in FIG. 10(b), and FIG. 10(cl) shows the head control timing in the NLQ mode.

In FIG. 10(b), consider the case where the wire arrangement of the distributed print head is arranged in accordance with the draft mode with a printing pitch of 1/120 inch. One column is distributed at 12 timings with A=1/120×1/12 inch. Furthermore, B=1/12
When set to 0XM inches (LM is an integer), it becomes Figure 1O (b
) pin M and pin (M+1) of odd and even pin rows
(However, LM is an odd number from 1 to 23) Since the integer multiple of the printing pitch is the even-odd pin row spacing of the head, the printing control timing is distributed over 12 printing control timings at the same timing. In the timing chart of (C), the printing pitch of l/120 inch is
Print with 7, pin M and pin (M11) (however, M is 1
The two pins (odd numbers from 23 to 23) control the head at the same timing.Furthermore, pin
1)/2XT8 (However, LM is an odd number from 3 to 23) The timing is delayed, and pin M is (
M2)/2xT8 (LM is an even number from 4 to 24)
Here, T8 is T7/12. In NLQ mode, as shown in Figure 10(d), the delay time between bins is T8, which is the same as in draft mode. At that time, pin 1, pin 2 , pin 9, pin 10, pin 17
The relationship between the wire arrangement of the head, the printing pitch, and the number of pins for simultaneous printing will be explained. FIG. 11 shows examples of dot-shaped printed characters in draft mode and NLQ mode and a timing chart for printing the characters. Now, for the sake of simplicity, the example of printed characters is limited to odd-numbered rows, and a case will be considered in which printing is performed only with odd-numbered pin rows as shown in FIG. 10(b). In the draft mode (when printing dots with a pitch of 1/120 inch as shown in Figure 11(a)), the 12 pins are evenly spaced while the head moves through the draft printing pitch as shown in Figure 11(b). When printing dots with a pitch of 1/360 inch as shown in Figure 11(c), for example pin 1 and Simultaneous firing occurs, such as pin 9 at the same timing. If you consider the even numbered pin rows in Figure 10 (b) in the same way, the wire arrangement in Figure 10 (b) has a maximum of 2 pins in draft and a maximum of 2 pins in NLQ. Simultaneous striking of 6 pins occurs.a As described above, when performing distributed printing of draft with a printing pitch of 17120 inch and NLQ with a printing pitch of 1/360 inch for the wire arrangement of the head shown in Figure 10 (b), the maximum in the draft In a 2-pin NLQ, simultaneous printing of up to 6 pins inevitably occurs.

Joint plate: As the printing pitch changes depending on the printing mode, the number N of simultaneous pins for each printing mode also changes depending on the wire arrangement of the head, so for example, as mentioned above, draft mode can achieve low noise, but NLQ mode can reduce noise. [Problem to be solved by the invention] Wire dot printers generally have multiple types of printing modes, that is, multiple types of character fonts and printing pitches, and the quality of printed characters is hindered. If a head with the same wire arrangement is used to print for each printing mode, the number of pins that can be driven at the same time changes depending on the mode, so there is a problem in that noise cannot be uniformly reduced [ Means for Solving the Problem] The present invention is an attempt to solve this problem. It is possible to print multiple types of fonts with different dot densities using a print head in which a plurality of pins are arranged in a direction oblique to the direction perpendicular to the direction of movement of the carriage. Since the number of pins to be driven at the same time changes depending on the dot density when printing, a printing timing control means is provided to change the driving time interval of the bins according to the number of bins to be driven simultaneously.[Operation] This will be explained in an example. Even if the number of bins to be driven simultaneously increases, the noise reduction effect can be obtained by lengthening the driving time interval of the bins. A print head control device according to an embodiment of the present invention will now be described.

FIG. 1 is a block diagram of a print head control device according to an embodiment of the present invention. In FIG. 1, 1 is a central processing unit (hereinafter abbreviated as CPU 7). ), 2 is an input/output unit (hereinafter abbreviated as μ10 section) which has an interface between each device; 3 is a character font read-only memory (hereinafter abbreviated as character phono ROM); and 4 is an oscillator. 5 is an address counter driven by the basic clock C generated by the oscillator 4, and a6 is a magnitude comparator driven by CP.
Print mode data f for switching character quality from the UI
7 is a distributed timing read-only memory (hereinafter abbreviated as distributed timing ROM) in which distributed timing is written.
The distributed timing is read out using the output e of the address counter 5 and the print mode data h for switching character quality from the CPU as an address. 8 is a latch unit that latches the output i of the distributed timing ROM 7, which is composed of a flip-flop. 9 indicates the timing at which the CPUI outputs the print data mo through the signal line d.9 is the latch clock J to the latch unit 8 based on the clock c1 which is the output e1 of the address counter 5 and the output of the oscillator 4 and is delayed by half a period from the basic clock C. In the shift register section that outputs
A distributed timing generation section 10 is constructed from these components, and each of the units 11, 12, and 13 delays the print data mO from the CPU 1 by one data period corresponding to one dot row using the inverted signal i of the output g of the magnitude comparator. Data m1, data m obtained by delaying data m1 by one data period
2. A latch circuit consisting of a flip-flop that outputs data m3 that is delayed by one data period from data m2.
14 is data ml, m2. A data selector 15 selects m3 by a select signal n from the CPUI. 15 is a latch ff1L consisting of a flip-flop that uses the output 0 of the data selector 14 as input data and the output 1 of the distributed timing generator as a latch clock. 16 is a distributed timing AN that ANDs the output l of the generation unit 10 and the output p of the latch unit 15 and outputs the head drive signal q.
The D circuit connects these to the FIFO section 17 and the head 18 drives the head 19 using the output of the latch section and the output q of the AND circuit. Effects are applied simultaneously and the number of bins N is N=1. 2. 3. In the actual measurement graph of the noise reduction effect expressed in relation to 6, a, if you want to obtain a noise reduction effect of 6 dB, the delay time T is as follows: When N = 1, T = 13 μs or more N
= 2 When T = 30 μs or more When N = 3 T = 42 /JS or more When N = 6 T = 117 μs or more is required Generally speaking, the smaller the number of bottles N is,
The larger the inter-dot delay time T, the higher the noise reduction effect t°C.
On the other hand, if the driving frequency f and N of the toilet head are determined, the noise effect will be N=1 when f=1kHz. T=42μs, 7. 8dB effect...T
/N=42 μ5 When f=2kHz, N=1. T=21μs, 6.6dB effect...T/N
=21 μ5 N=2. T=42μs, 6. 8dB effect...T
/N=21 μ5 When f=3kHz, N=1. T=14. us, 6. 1dB effect...
T/N= 1 4 μ5 N=2. T=28μs, 5.9dB effect...T/N
=14 μ5 N=3. T=42μs, 6. OdB effect...T
/N=14 μ5 When f=4kHz, N=1. T=10μs, 5. 6dB effect...
・T/N=10 μ5 N=2. '[' = 5.5dB effect in 21μs...T/
N=10 μ5 N=3. 5.2dB effect at T=31μs...T/N=
10 μs, so if the T/N is the same, the noise reduction effect will hardly change. In contrast, the fact that noise reduction cannot be achieved uniformly is compensated for by designing the do-to-met delay time T within a range that allows the noise reduction effect to be obtained, as shown in FIG.

When the head wire arrangement shown in FIG. 10(b) is used, the printing pitch is 1 as described in the conventional example above.
Simultaneous printing of N2 occurs in the draft mode of /120 inch, and N = 6 occurs in the NLQ mode with a printing pitch of 1/360 inch, and as shown in Figure 2, the noise reduction effect in the NLQ mode is better than in the draft mode. Na(t So, N
In the LQ mode, design should be made with an inter-dot delay time T that has the same effect as the draft mode as shown in Figure 3 without changing N (in this example, in the NLQ mode, the time to print 1/360 inch is T9, In other words, 1/120 inch is 3 x T9
The delay time between pins is 3xT9/12=Tl'
Figure 4 (a) is a circuit for one pin of the head driver 18.
FIG. 4(b) is a timing chart of signals that drive the head driver 18. In FIG. 4(a), transistors 21, 22, and a diode 23 are connected to both ends of the head coil 20.
Although the emitter of the transistor 22 is connected to the collector of the transistor 26 through the resistor 25 and the emitter of the transistor 22 is grounded, the operation of the print head control device constructed as above will be explained below. Figure 5 shows the dot pattern of the head controlled by the print head control device of the present invention. In Figure 5, the dot pattern of the head is such that the odd numbered pins out of 24 pins are in the first column, the even numbered pins are in the second column, and the same column. Even if pin N and pin (N+2) of the 12 pins in each column are shifted by 1/120 x 1/12 inch in the printing line direction, 1/120 inch is the character Pin N and pin (
In the following explanation, even if N+1) is driven at the same timing, that is, even if the interval in the printing row direction of the first and second columns is an integral multiple of 1/120 inch, the 12 bins in the same column will be driven at the same timing. For ease of control, the lower 8 bins are set as L block and the upper 4 pins are set as H block. However, Figure 6(a) shows that 24 bins are used for the output signal of the distributed timing generator when the print mode is draft 10 cpi. FIG. 6(b) is a timing chart showing the timing for 24 bins of the output signal 1 of the distributed timing generator, L Tl is the basic cycle for printing one dot, T2 is the ON time of the transistor 21 in FIG. 4(a) [T3 is the ON time of the transistor 22 in FIG. 4(a). +i T in each print mode
Even if the length of 1 is different, the distributed timing ROM 7 has a total of 24 types of basic cycle signals corresponding to each pin and each transistor written in advance, and is read out at the address generated by the address counter 5. Cutting board
For the timing data of the distributed timing ROM 7, design the distributed timing by considering the inter-dot delay time T and the number of simultaneous printing bins N. Figure 7 shows the address map of the distributed timing ROM 7. Draft and N L Q
(Near Letter Quality) Number of letters per inch: 10, 12, 15, 17cp
4 types of i: The print direction of the head is the forward direction (hereinafter referred to as G).

There are two types of print modes: 1) and 2 types (hereinafter abbreviated as RETURN). Corresponding to each, distributed timing data is written in hexadecimal numbers every 1000 addresses up to a total of FFFF addresses. Although the selection is made by the mode data signal, T1 in Fig. 6 is a force whose length differs depending on each printing mode (the magnitude comparator 6 adjusts it to each printing mode and sets the address counter 5 to all zeros after the T1 time has elapsed). Maximum 102
Even if it is 4 μs, FIG. 8 is a timing chart showing the output latch timing of the distributed timing ROM 7. The switching time T4 of the address e is T4=250 nS, and the transistor 22 is turned on from the distributed timing ROM 7 by the address e in a period of 1 μs. The lower 8 bits of the signal that turns on the transistor 21 (hereinafter abbreviated as PL data), the upper 8 bits of the signal that turns on the transistor 22 4-bit data (hereinafter abbreviated as CH data 7)), upper 4-bit data of the signal that turns on the transistor 21 (hereinafter abbreviated as PH data 4), are sequentially output, and L T5 is distributed. Timing ROM7
Since the output delay time of is about 150nS, CL,
PL, C)L The timing T6 to latch PH data is T6=200n so that T5<T6<T4.
Even if S, these latch clocks jl, j2
．． j3. j4 is e1.j4 output from the address counter in the shift register 9. The latch unit 8 receives the CL data of the output i of the distributed timing ROM 7, which is generated from the C1 output from the oscillator 4.

PL data, CH data, PH data, latch clock jl, j2. j3. By latching them by j4 and further latching them at the rising timing of el, each becomes a 12-bit distributed timing signal.
I is generated. These outputs have an accuracy of 1 μs. Figure 9 is a timing chart of the FIFO section. Character printing modes are draft/NLQ and 10, 12, 15.
, 17cpi, and among these types, for example, as shown in Figure 9, there are 8 types with a printing dot spacing of 17,432 inches.By the way, the dot pattern spacing of the head is 1/120 inch, so 1/ 120 inches
The dispersion timing for dividing into two is 4 bits of print data mO with a print dot interval of 1/432 inch from the CPUI.
First, obtain data delayed for 1 day, 2 days, and 3 data periods, such as ml, m2, and m3, for data mO. Input data 0 selected by select signal n from CPUI to data selector 14. In the case of Figure 9, pins 1 to 8, pin 9
-14, pins 15-20, and pins 21-24, the respective print data are mo, ml, m2. Even if it supports m3
Here, if the print data interval is fixed at 1/120 inch, this data selector 14 and flip-flop group 11
, 12, 13 are the required 1 to m.

The output of the data selector 14 is that the print data of each of the 24 pins input to the latch unit 15 is latched by the distributed timing signal shown in FIG. The head drive signal q is obtained by ANDing the distributed timing signal 1 with the AND circuit 16.
So 1. As shown in Figure 4, first, let q be both h
When set to high, transistors 21 and 22 are turned on, and current flows through the head coil 20 and increases according to the time constant.Next, when k is set to low, 21 is turned off and current flows from the diode 23 to the head coil 20. niq
When set to low, the current gradually goes to zero.A Wire dot printers that are driven by electromagnetic force have a two-stage drive that switches both ends of the head coil to drive the wire at high speed and with low power consumption. k, q
In the print head control device shown in FIG. 5 of this embodiment, which is driven by head drive signals with two types of timing, when the print mode is draft T10 cpi, the inter-dot delay time T = 36 μs, the number of simultaneous printing bins N = 2, NLQlo
In the case of cpi, even if the inter-dot delay time T = 117 μs and the number of simultaneous pins N = 6, the noise reduction effect will be 6°5d & 6. At 2 dB, as shown above, in this example, at draft 10 cpi, the number of simultaneous firing bottles N is /J%+; NLQ 10 c p
With the i, a noise reduction effect of approximately 6 dB can be obtained by setting the inter-dot delay time T to a minimum, and by using a distributed timing ROM, the inter-dot delay time T and head drive frequency are taken into account for various printing modes. The timing of distributed printing can be easily set and changed [Effects of the Invention] As described above, the present invention has the following advantages: Dispersion timing for correcting the inclination of the pin row in the direction perpendicular to the direction of movement of the carriage on which the print head is mounted. By changing the print delay time of the timing stored in ROM, that is, the drive timing of adjacent pins in the same row of odd-numbered pin rows and even-numbered bin rows, depending on the print mode, noise can be reduced even in wire dot printers with multiple print modes. is now possible

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an impact dot printer according to an embodiment of the present invention. FIG. 2 is a graph of the noise reduction effect versus the inter-dot delay time T. FIG. 3 is a graph of the inter-dot delay time T versus the noise reduction effect. Number of pins driven simultaneously with N
FIG. 4(a) shows the head driver 18 with a glass ratio of 1.
FIG. 4(b) is a timing chart of the signal that drives the head driver 18, and FIG. 5 is a dot pattern diagram of the head controlled by the print head control device of the present invention. FIG. 6(a) is a dispersion diagram. A timing chart showing the timing for 24 pins of the output signal of the timing generation section, FIG. 6(b) is a timing chart showing the timing for 24 pins of the output signal 1 of the distributed timing generation section,
7 is an address map of the distributed timing ROM 7, FIG. 8 is a timing chart showing the output latch timing of the distributed timing generation ROM 7, FIG. 9 is a timing chart of the FIFO section, and FIG. 10 (a) is the draft and N
An explanatory diagram of the LQ printing pitch. Fig. 10 (b) is an explanation of the wire arrangement of the conventional distributed print head. Fig. 10 (C) and Fig. 10 (d) are timings showing the control timing of the conventional distributed print head. Charts, Figures 11(a) and 11(b) are explanations of the draft printing timing @ Figures 11(c) and 11(d) are illustrations of the NLQ printing timing and are read out Dedicated memory 9...Shift register section Mining generation section 12...Latch section 14...Data selector 16...AND circuit 18...Head driver 20...Head coil 22...Transistor 24...・Resistor 26...Transistor 7...Dispersion timer 8...Latch section 0...Dispersion tight...Latch section 3...Latch section 5...Latch section 7...FIFO section 9. ... Head... Transistor 3... Diode 5... Resistor Name of agent Patent attorney Shigetaka Awano 1 person 1... Central processing unit 2... Input/output section 3... Text font reading Dedicated memory 4...Oscillator 5.
...Address counter 6...Magnitude comparator diagram (α) @'+a Diagram exit F: Row 2 diagram dot spacing positive time ()LS) 1st threshold (α) (>) Bisi ζ- -------------[-11111cho-goko2
1124-Shi1111-''- Figure Figure 11J2 pin 19, 20 bit 7'']]''Cho down''-]- Figure 1 (/2bit) 1 (f2brt) T==== =T= Figure (Q) → EF direction L) → EP direction No. 1 (C) "-m- "- Figure (Q) (b)

Claims (1)

[Claims] An impact dot printer that prints by selecting one type of font from a plurality of different dot densities, wherein a plurality of pins are arranged at an angle with respect to a direction perpendicular to the moving direction of a carriage. an impact dot, comprising: a print head that is printed, and a print timing control means that changes the driving time interval of the pins according to the number of simultaneously driven pins of the print head that changes according to the type of font to be printed. printer.