JPH0436148Y2 - - Google Patents

Info

Publication number
JPH0436148Y2
JPH0436148Y2 JP10155386U JP10155386U JPH0436148Y2 JP H0436148 Y2 JPH0436148 Y2 JP H0436148Y2 JP 10155386 U JP10155386 U JP 10155386U JP 10155386 U JP10155386 U JP 10155386U JP H0436148 Y2 JPH0436148 Y2 JP H0436148Y2
Authority
JP
Japan
Prior art keywords
base material
layer base
stamp display
wiring board
outer layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10155386U
Other languages
Japanese (ja)
Other versions
JPS636771U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10155386U priority Critical patent/JPH0436148Y2/ja
Publication of JPS636771U publication Critical patent/JPS636771U/ja
Application granted granted Critical
Publication of JPH0436148Y2 publication Critical patent/JPH0436148Y2/ja
Expired legal-status Critical Current

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  • Structure Of Printed Boards (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は多層印刷配線板に関し、特に外層基材
表面の捺印表示個所に対向する下層の内層基材の
導体箔が除去された多層印刷配線板に関する。
[Detailed description of the invention] [Field of industrial application] The present invention relates to a multilayer printed wiring board, and particularly to a multilayer printed wiring board in which the conductive foil of the lower inner layer base material opposite to the stamped area on the surface of the outer layer base material has been removed. Regarding the board.

〔従来の技術〕[Conventional technology]

従来、多層印刷配線板(以後、多層配線板と略
称)は、第3図に示す如く導体箔3aを有する内
層基材3と外層基材2とから構成されている。ま
た内層基材3の導体箔3aの表面は外層基材の2
との接着力を強化するため黒色を呈する粗面化処
理を施している。そのため外層基材2の表面の捺
印表示個所4から内層基板3を透視すると、多層
基材2が黒化して見える個所に捺印表示を施して
いる。一方、捺印表示のインクは(イ)多層配線
板1の外層基材2に対して捺印性が良い、(ロ)
捺印表示個所の下地色に対する視認性が良い、
(ハ)電子部品搭載後の溶剤による洗浄において
も判読性が劣化しない、等の要求から黒化処理し
たものが使用されいている。
Conventionally, a multilayer printed wiring board (hereinafter abbreviated as a multilayer wiring board) is composed of an inner layer base material 3 and an outer layer base material 2 having a conductive foil 3a, as shown in FIG. Further, the surface of the conductor foil 3a of the inner layer base material 3 is the same as that of the outer layer base material 2.
The surface is roughened to give it a black color in order to strengthen its adhesion. Therefore, when the inner layer substrate 3 is seen through the stamp display location 4 on the surface of the outer layer base material 2, the stamp display is applied to a portion where the multilayer base material 2 appears blackened. On the other hand, the ink for marking (a) has good marking properties on the outer layer base material 2 of the multilayer wiring board 1; (b)
Good visibility of the base color of the stamp display area,
(c) Blackened materials are used because of the requirement that readability does not deteriorate even when cleaning with a solvent after electronic components are mounted.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

上述した従来の多層配線板では、捺印表示個所
の下地の色と捺印表示インクの色がほぼ同色の黒
色同志であるため捺印表示が判読しにくい欠点が
ある。
The above-mentioned conventional multilayer wiring board has a drawback that the stamp display is difficult to read because the color of the base of the stamp display area and the color of the stamp display ink are almost the same color, black.

本考案の目的は、捺印表示の判読が容易でしか
も部品搭載後の判読性も劣化しない多層印刷配線
板を提供することにある。
An object of the present invention is to provide a multilayer printed wiring board in which the markings are easy to read and the readability does not deteriorate after parts are mounted.

〔問題点を解決するための手段〕[Means for solving problems]

本考案の多層印刷配線板は、外層基材表面の捺
印表示個所に対向する下層の内層基材の導体箔が
除去され、かつ外層基材表面の捺印表示個所に捺
印表示が施されて構成される。
The multilayer printed wiring board of the present invention is constructed by removing the conductor foil of the lower inner layer base material that is opposite to the stamp display location on the surface of the outer layer base material, and applying a stamp display to the stamp display location on the surface of the outer layer base material. Ru.

〔実施例〕〔Example〕

次に、本考案の実施例について図面を参照して
説明する。第1図、第2図は本考案の一実施例の
多層配線板およびその構成に用いる内層基材の斜
視図である。図中、参照符号14は多層配線板1
1の外層基材12表面の捺印個所である。
Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are perspective views of a multilayer wiring board according to an embodiment of the present invention and an inner layer base material used in its construction. In the figure, reference numeral 14 indicates multilayer wiring board 1
This is the stamping location on the surface of the outer layer base material 12 of No. 1.

まず第1図に示した捺印表示個所14の下層の
内層基材13の導体箔13aを公知のフオトエツ
チング法により第2図に示す如く他の導体箔除去
部20,30の形成と同時に除去して導体箔除去
部40を設ける。次に内層基材13の導体箔13
aを粗面化処理し、さらに公知の熱プレスなどの
加熱、加圧手段により外層基材12、内層基材1
3を積層一体化し第1図の如く構成する。次に外
層基材12の捺印表示個所14にロツト番号など
の捺印表示14aを黒色のインクで施す。このよ
うに構成した第1図の多層配線板11の捺印表示
個所14から下層の内層基材13を透視すると、
捺印表示個所14に対向する下層の内層基材13
の導体箔13aが除去されているため捺印表示1
4aの黒色と下地色との色彩が明確に違つて見え
る。
First, the conductor foil 13a of the inner layer base material 13 below the stamp display area 14 shown in FIG. 1 is removed by a known photo-etching method at the same time as the other conductor foil removal parts 20 and 30 are formed as shown in FIG. A conductor foil removal section 40 is provided. Next, the conductor foil 13 of the inner layer base material 13
A is subjected to surface roughening treatment, and further heated and pressed by a known heat press or the like to form an outer layer base material 12 and an inner layer base material 1.
3 are laminated and integrated to form a structure as shown in FIG. Next, a stamp 14a such as a lot number is applied to the stamp display location 14 of the outer layer base material 12 using black ink. When looking through the lower inner layer base material 13 from the stamp display location 14 of the multilayer wiring board 11 of FIG.
Lower inner layer base material 13 facing the stamp display location 14
Since the conductor foil 13a has been removed, the seal indication 1
The black color of 4a and the base color appear clearly different.

〔考案の効果〕[Effect of idea]

以上説明したように本考案は、外層基材表面の
捺印表示個所に対抗する下層の内層基材の導体箔
が除去され、かつ外層基材の表面の捺印表示個所
に捺印表示が施されているので、(1)捺印表示
インクの色と下地色が違うので捺印表示の判読が
容易となる。また(2)インクは従来の選別され
たものを用いることができるので電子部品搭載後
の判読性も劣化しないので不良解析が容易になる
などの効果が得られる。
As explained above, in the present invention, the conductor foil of the lower inner layer base material that opposes the stamp display location on the surface of the outer layer base material is removed, and the stamp display is applied to the stamp display location on the surface of the outer layer base material. Therefore, (1) the color of the seal display ink and the base color are different, making it easier to read the seal display. Furthermore, (2) since the conventionally selected ink can be used, the readability after mounting electronic components does not deteriorate, so that it is possible to obtain effects such as facilitating failure analysis.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の多層配線板の斜視
図、第2図は本考案の一実施例に用いる内層基材
の斜視図、第3図は従来例の多層配線板の斜視図
である。 1,11……多層配線板、2,12……外層基
材、3,13……内層基材、3a,13a……内
層基材の導体箔、4,14……捺印表示個所、1
4a……捺印表示、20,30,40……導体箔
除去部。
Fig. 1 is a perspective view of a multilayer wiring board according to an embodiment of the present invention, Fig. 2 is a perspective view of an inner layer base material used in an embodiment of the invention, and Fig. 3 is a perspective view of a conventional multilayer wiring board. It is. DESCRIPTION OF SYMBOLS 1, 11... Multilayer wiring board, 2, 12... Outer layer base material, 3, 13... Inner layer base material, 3a, 13a... Conductor foil of inner layer base material, 4, 14... Stamp display location, 1
4a... Stamp display, 20, 30, 40... Conductor foil removed portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外層基材表面の捺印表示個所に対向する下層の
内層基材の導体箔が除去され、かつ、前記外層基
材表面の捺印表示個所に捺印表示が施された多層
印刷配線板。
A multilayer printed wiring board in which a conductive foil of a lower inner layer base material opposite to a stamp display location on the surface of the outer layer base material is removed, and a stamp display is applied to the stamp display location on the surface of the outer layer base material.
JP10155386U 1986-07-01 1986-07-01 Expired JPH0436148Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10155386U JPH0436148Y2 (en) 1986-07-01 1986-07-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10155386U JPH0436148Y2 (en) 1986-07-01 1986-07-01

Publications (2)

Publication Number Publication Date
JPS636771U JPS636771U (en) 1988-01-18
JPH0436148Y2 true JPH0436148Y2 (en) 1992-08-26

Family

ID=30972387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10155386U Expired JPH0436148Y2 (en) 1986-07-01 1986-07-01

Country Status (1)

Country Link
JP (1) JPH0436148Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09116243A (en) * 1995-10-19 1997-05-02 Alps Electric Co Ltd Circuit board

Also Published As

Publication number Publication date
JPS636771U (en) 1988-01-18

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