JPH0436332U - - Google Patents

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Publication number
JPH0436332U
JPH0436332U JP7910890U JP7910890U JPH0436332U JP H0436332 U JPH0436332 U JP H0436332U JP 7910890 U JP7910890 U JP 7910890U JP 7910890 U JP7910890 U JP 7910890U JP H0436332 U JPH0436332 U JP H0436332U
Authority
JP
Japan
Prior art keywords
fet
drive circuit
isolated amplifier
chopper circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7910890U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7910890U priority Critical patent/JPH0436332U/ja
Publication of JPH0436332U publication Critical patent/JPH0436332U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは本考案の一実施例、bは各部の動作
波形、第2図a,bは従来例を示す。 FET,FET……ジヤンクシヨン型FE
T、C,C……コンデンサ、D,D……
ダイオード。
1A shows an embodiment of the present invention, FIG. 1B shows operation waveforms of various parts, and FIGS. 2A and 2B show a conventional example. FET 1 , FET 2 ... Junction type FE
T, C 1 , C 2 ... Capacitor, D 1 , D 2 ...
diode.

Claims (1)

【実用新案登録請求の範囲】 入力側および出力側にそれぞれジヤンクシヨン
型のFET,FETが用いられ、かつFET
,FETのゲートに正電圧印加防止用のダイ
オードD,Dがそれぞれ接続された構成の絶
縁増幅器チヨツパ回路用FETドライブ回路にお
いて 前記ダイオードD,Dに前記FET,F
ETのゲート−ソース間の容量を打ち消すコン
デンサC,Cをそれぞれ並列接続したことを
特徴とする絶縁増幅器チヨツパ回路用FETドラ
イブ回路。
[Claims for Utility Model Registration] Junction-type FETs 1 and 2 are used on the input side and output side, respectively, and the FET
1. In an FET drive circuit for an isolated amplifier chopper circuit, the diodes D 1 and D 2 for preventing positive voltage application are connected to the gates of the FET 2 , respectively.
1. A FET drive circuit for an isolated amplifier chopper circuit, characterized in that capacitors C 1 and C 2 are connected in parallel to cancel the capacitance between the gate and source of ET 2 .
JP7910890U 1990-07-25 1990-07-25 Pending JPH0436332U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7910890U JPH0436332U (en) 1990-07-25 1990-07-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7910890U JPH0436332U (en) 1990-07-25 1990-07-25

Publications (1)

Publication Number Publication Date
JPH0436332U true JPH0436332U (en) 1992-03-26

Family

ID=31622976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7910890U Pending JPH0436332U (en) 1990-07-25 1990-07-25

Country Status (1)

Country Link
JP (1) JPH0436332U (en)

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