JPH04364531A - Microprocessor - Google Patents

Abstract

PURPOSE:To offer the microprocessor which can detect a runaway immediately in all instruction processes including a branch instruction and an interruption instruction without depending upon firmware. CONSTITUTION:A comparison control circuit (instruction decoding circuit) 15 which detects the branch instruction, interruption instruction, etc., is provided and when, for example, the branch instruction is detected, its branch destination address is saved in a storage circuit 12 before the execution of the instruction; and an instruction is fetched from the same address again and when the instruction indicates relative branching, an address generating circuit 11 generates a branch destination address according to the address that an address counter 13 indicates before update and fetched displacement and saves the branch destination address in the address counter 13. When the instruction indicates absolute branching, on the other hand, the fetched address is saved in the address counter 13 and a comparing circuit 14 compares the value in the address counter 13 with the value in the storage circuit 12 to detect the runway of a program.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor incorporating a program runaway detection circuit.

0002

[Background Art] With the advancement of semiconductor technology, microprocessors, peripheral control LSIs, and memory LSIs have become available at very low prices, and it is now possible to construct relatively high-performance personal computers simply by appropriately combining these. It became so. In particular, the performance of microprocessors, which serve as the control center of personal computers, has improved markedly, with not only 8-bit, 16-bit, and 32-bit data processing, but even 64-bit processing and built-in caches have recently appeared.

By the way, the above-mentioned personal computer stores programs in its built-in memory, and executes data processing while reading out the contents according to the address set in the program counter. The program counter indicates the memory address of the next instruction to be executed.
It is updated every time execution of an instruction is completed, and the next address is set. In order to detect program runaway during normal data processing in such a system, for example, a watchdog timer relies on firmware.
Runaway detection was performed by including an instruction to reset a timer in the program, and determining that a runaway occurred when the value of the timer (the counter that constitutes it) exceeded a certain set value.

0004

Conventionally, runaway detection has been performed by indicating a certain constant value of the count value of a timer, and therefore runaway detection cannot be performed immediately.

[0005] To solve this problem, it is possible to consider hardware that has a circuit inside the microprocessor that checks the value of the program counter by comparison, and immediately detects runaway without depending on firmware.

However, even if instructions stored in memory are executed sequentially, a means for prohibiting the compare operation is required when processing branch instructions or interrupt instructions, and therefore runaway detection cannot be performed. Even if it ran out of control, it could not be detected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor that can immediately detect runaway in all instruction processing, including branch instructions and interrupt instructions, without depending on firmware.

[0008]

[Means for Solving the Problems] The microprocessor of the present invention has an address calculation circuit that calculates the address of the next instruction to be executed based on the number of bytes of the fetched instruction and the address before updating, before executing the instruction. a memory circuit for storing the address calculated by the address calculation circuit; and a comparison circuit for comparing the updated address of the program counter with the address stored in the memory circuit after execution of the instruction. The present invention is characterized by comprising a comparison control circuit that determines the type of instruction to be executed and controls the comparison operation by the comparison circuit according to the determination result.

[0009] Furthermore, the present invention provides that when an instruction that changes the address sequence, such as a branch instruction or an interrupt instruction, is detected by the comparison control circuit, the destination address of the change is stored in the storage circuit before the execution of the changing instruction. At the same time, the instruction is fetched again from the same address, and if it is a relative branch, the branch destination address is generated by the above address calculation circuit based on the address before update and the fetched displacement, and is set in the program counter. , if it is an absolute branch, the fetched address may be set in the program counter, and then a compare operation is executed by a comparison circuit between the contents of the program counter and the contents of the storage circuit, thereby detecting a program runaway. Features.

0010

[Operation] The address calculation circuit adds the number of bytes of the fetched instruction and the value of the program counter before updating, calculates the address of the next instruction to be executed, and saves it in the storage circuit. Next, the program counter is updated as the instruction is executed, and the updated address is compared with the address saved in the storage circuit in a comparison circuit. If there is a mismatch, it is determined that the program has runaway, and the microprocessor stops operating.

However, if the fetched instruction is a branch instruction, the branch destination (jump destination) address is saved in the memory circuit before the branch instruction is executed, and the instruction (branch instruction) is fetched again from the same address. Then, the address indicated by the instruction is saved in the program counter, and runaway detection is performed by a compare operation by a comparator circuit. This makes it possible to immediately detect program runaway in all instruction processing including branch instructions.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an example of the configuration of a personal computer in which the present invention is used.

In the figure, 1 is a microprocessor (μ
CPU), reads the program stored in system RAM2 or the program (BIOS program) stored in BIOS-ROM3 (basic input/output system), and performs arithmetic control or control of each input/output device connected to the system. . Reference numerals 4, 5, and 6 are input/output devices, including a keyboard (KB) for inputting data, a floppy disk device (FDD) for external storage, and a display device (CRT) for displaying data. These input/output devices are all controlled by the BIOS program, and are all programmable input/output controllers by the microprocessor 1, such as a keyboard controller (KBC) 7, a floppy disk controller (FDC) 8, and a display controller (CRTC).
9.

FIG. 2 is a block diagram showing an embodiment of the present invention, and shows only the portions related to the present invention extracted from the internal configuration of the microprocessor 1 shown in FIG. In the figure, 11 is an address generation circuit, which determines the address to be set in the address counter 13. 1
2 is a storage circuit in which the address calculated by the address generation circuit 11 is saved. 13 is an address counter (program counter), which indicates the address where the next instruction to be executed is stored.

A comparison circuit 14 compares the address saved in the storage circuit 12 with the value set in the address counter 13. Reference numeral 15 denotes a comparison control circuit, which controls the compare operation by the comparison circuit 14, and mainly consists of control circuits for execution of instruction fetch, such as an instruction decode circuit and a timing clock generation circuit.

The operation of the embodiment of the present invention will be explained below. First, in this embodiment, the comparison control circuit 15 (a built-in decoding circuit) shown in FIG. is saved in the memory circuit 12,
The instruction is read out again, and the jump destination address indicated by the instruction is compared with the address saved in the memory circuit 12, and if they do not match, it is regarded as a runaway.

That is, at the time of a branch instruction, the value to be set in the address counter 13 (jump address) according to the instruction is calculated and saved in the memory circuit 12, and then the same instruction is read out again and the address is calculated. The value is saved in the address counter 13, and the value in the memory circuit 12 and the value in the address counter 13 are compared. At this time, if they match, normal operation will proceed; if they do not match, it will be considered a runaway.

Next, the operation of the configuration shown in FIG. 2 will be explained in more detail. First, before executing a fetched instruction (to the microprocessor 1), the address generation circuit adds the number of bytes of the instruction and the value of the address counter 13 before updating (i.e., the address of the fetched instruction).
1, and the result of the addition is saved in the memory circuit 12. At this point, the memory circuit 12 indicates the address to be executed next to the instruction to be executed.

Next, as the instruction is executed, the address counter 1
Update 3. As a result, under normal conditions without program runaway, the value of the address counter 13 should indicate the address of the next instruction to be executed, and should be the same value as the memory circuit 12. Therefore, under the control of the comparison control circuit 15, the comparison circuit 14 compares the value of the storage circuit 12 and the value of the address counter 13, and if they do not match, it is determined that the program has runaway.

The above describes the detection of program runaway during normal instruction execution (when instructions are executed sequentially), but when executing instructions that change the address sequence such as branch instructions and interrupt instructions, for example, branch instructions. , program runaway is detected as follows.

That is, when executing a branch instruction, the branch destination address is saved in the storage circuit 12 before executing the branch instruction. Furthermore, before executing the branch instruction, fetch the instruction again from the same address (if normal, the same branch instruction), and if the instruction is a relative branch, compare the value of the address counter 13 before updating and the displacement indicated by the fetched instruction. is added in the address generation circuit 11 to generate a jump destination address and saved in the address counter 13. On the other hand, if the instruction is an absolute branch, the address (jump destination address) indicated by the fetched instruction is saved in the address counter 13 as is.

In this state, the comparison control circuit 15 uses the comparison circuit 14 to compare the contents of the storage circuit 12 and the address counter 13.
Runaway detection is performed by comparing with the contents of .

It is also possible to prevent program runaway by adding a circuit that stops the operation of the microprocessor in response to the compare output from the comparison circuit 14 or returns to the initial routine.

[0024]

According to the present invention, program runaway can be immediately detected in all instruction processing including branch instructions, thereby improving reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a personal computer in which the present invention is used.

FIG. 2 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

11...address generation circuit (address calculation circuit), 12...
Memory circuit, 13... Address counter (program counter), 14... Comparison circuit, 15... Comparison control circuit.

Claims (2)

[Claims] [Claim 1] In a microprocessor that stores a program in memory and executes its contents according to an address set in a program counter, prior to executing an instruction, a microprocessor that stores a program in a memory and executes the program based on the number of bytes of the fetched instruction and the address before updating. an address calculation circuit that calculates the address of the next instruction to be executed; a storage circuit that stores the address calculated by the address calculation circuit; and an updated address of the program counter and the storage circuit after the instruction is executed. and a comparison control circuit that determines the type of instruction to be executed and controls the comparison operation by the comparison circuit according to the determination result. Features a microprocessor. 2. When an instruction to change the address sequence is detected by the comparison control circuit, the destination address to be changed is stored in the storage circuit before execution of the change instruction, and the instruction is fetched again from the same address. death,
If it is a relative branch, the branch destination address is generated by the above address calculation circuit based on the pre-update address and the fetched displacement and set in the program counter, and if it is an absolute branch, the branch destination address is 1. A runaway program is detected by setting an address in the program counter and then causing the comparison circuit to perform a compare operation between the contents of the program counter and the contents of the storage circuit.
Microprocessor as described.