JPH0436459B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a field effect transistor, and particularly to a structure of a shot barrier gate type field effect transistor suitable for high frequency operation and a method for manufacturing the same.

[Technical background of the invention and its problems]

Gallium arsenide (GaAs) semiconductor devices have superior high-speed performance compared to silicon semiconductor devices, and research and development thereof has been rapidly progressing in recent years. Especially GaAs
Schottky barrier-gate field effect transistors (GaAs MES FETs) are increasingly being put into practical use as microwave devices, and are also one of the most important components of GaAs ICs.

In order to improve the performance of the GaAs MES FET mentioned above, it is necessary to reduce parasitic resistance and capacitance as much as possible. In particular, it is important to keep the channel series resistance between the source and gate electrodes low.

However, in a GaAs MES FET, for example, as shown in FIG. 1, an n-type semiconductor layer 2 is formed on a semi-insulating GaAs substrate 1 by ion implantation, and then an n + implantation layer 3 in the source region and an n ⁺ implantation layer 3 in the drain region are formed. It has a structure in which an n ⁺ injection layer 4 is provided, and a gate electrode 5 is provided on an n-type semiconductor layer 2 sandwiched between both regions. A source electrode 6 and a drain electrode 7 are provided in both regions, respectively. In the structure described above, it is necessary to allow for errors due to mask alignment in each photo-etching process, and due to limitations of photo-etching technology, it is necessary to provide a certain distance between the source and the gate. Therefore, as described above, it is difficult to reduce the series resistance by the n-type active layer 2, and even if the gate length is made submicron, the performance does not improve as much as expected.

Further, the source electrode 6 and the drain electrode 7 are usually
A gold-germanium (Au-Ge) alloy-based electrode is used, but the formation of this electrode always requires a process of alloying the electrode metal with GaAs crystal, which is called an alloy. During this alloying process, the electrode metal often reacts unevenly, causing island-like aggregation (ball-up), which does not lower the contact resistance sufficiently and makes it difficult to form an electrode with a smooth surface.
This has been one of the obstacles to the formation of integrated circuits (ICs) that use multiple MES FETs.

Furthermore, as a matter of course, the metals used for the gate electrode, which forms a shotgun junction, and the source and drain electrodes, which form ohmic contact, are of different types.

[Purpose of the invention]

The present invention eliminates the drawbacks of conventional manufacturing methods and aims to provide a novel method for manufacturing shot barrier gate field effect transistors. According to the invention, a gate electrode metal layer;
Since the source and drain electrode metal layers can be formed of metal layers having the same structure and can be formed at the same time, the manufacturing process can be significantly shortened.

[Summary of the invention]

A method for manufacturing a field effect transistor according to the present invention includes a step of forming an active layer on the main surface of a high resistivity semiconductor substrate, a step of depositing a germanium thin film on the source and drain regions on the surface of the active layer, and a step of depositing a germanium thin film on the source and drain regions on the surface of the active layer. a step of laminating at least one layer of an insulating film for a spacer on the surface of an active layer containing the active layer; a step of heat-treating the semiconductor substrate together with the insulating film for a spacer; a step of sequentially or simultaneously forming second openings in correspondence with the regions where the source and drain regions are to be formed, and depositing at least one metal layer for an electrode from above the insulating film for a spacer; A step of simultaneously forming a gate electrode layer on the active layer exposed in the first hole and a source and drain electrode in the second hole, and a step of simultaneously forming a metal layer for electrodes deposited outside the desired area. Further, the first layer of the spacer insulating film is an insulating film doped with an impurity that becomes a donor for germanium. Further, the heat treatment is performed in, for example, an atmospheric gas containing As.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained in order of steps with reference to the drawings.

First, Si ions (Si ⁺ ) are selectively implanted into the MES FET formation region into the semi-insulating GaAs substrate 11 at an acceleration energy of 100 keV and a dose of 3.5×10 ¹² cm ^-2 .
An injection layer 12' is formed (FIG. 2).

Next, a CVD SiO ₂ film 13 with a thickness of about 3000 Å and a thickness of about 1 μm is deposited.
A thick photoresist film 14 is laminated and is used as an ion shielding mask to perform selective ion implantation into the region 15' where the source region is to be formed and the region 16' where the drain region is to be formed. In this ion implantation, Si ⁺ was accelerated at an energy of 120 keV and a dose of 2.5×10 ¹³ cm ^-2
It is then applied in a multi-stage injection at 250 keV at 2.5 x 10 ¹³ cm ^-2 . Next, germanium (Ge) 17 is deposited to a thickness of approximately 700 Å from above the CVD SiO ₂ film 13 and photoresist film 14 used for the ion shielding mask, and a Ge film 17' is placed on the mask film for the source and drain regions. Ge thin film 17 on each area planned to be formed,
17 (Figure 3).

Next, the Ge film 17' on the mask is removed by lift-off, and the CVD SiO ₂ film 13 is also removed (FIG. 4).

Next, arsenic-doped silicon dioxide film (As SG
A film) 18 is deposited to a thickness of about 5000 Å and annealed at 850°C for 15 minutes in an Ar gas atmosphere containing As to form the n ⁺ injection layer 15 in the areas where the injection layer 12' and the source and drain regions are to be formed. ', 16' are activated to form the active layer 12, source region 15, and drain region 16 (FIG. 5).

Note that the above-mentioned annealing also serves as a heat treatment performed after the formation of the Ge thin film as claimed in the claims, and as a result, Ge and GaAs react, and As is also formed in the Ge thin film from the AsSG film 18. Highly doped.

Next, a photoresist film 19 is deposited, and the gate is positioned at a predetermined position sandwiched between the source and drain regions using a mask in which the gate, source, and drain patterns are integrally formed. After aligning the masks as shown in FIG. 6, holes corresponding to the gate, source, and drain are formed by photoetching, and the underlying AsSG film is etched through these holes to expose the GaAs and Ge surfaces (see Figure 6). ).

Next, a titanium (Ti) metal layer with a thickness of about 1000 Å and an aluminum (Al) metal layer with a thickness of about 4000 Å are deposited, and a titanium metal layer 21g and an aluminum metal layer 22g are formed in the area where the gate electrode is to be formed. A source electrode layer 23s consisting of a titanium metal layer 21s and an aluminum metal layer 22s in the region where the source electrode is to be formed, and a titanium metal layer 21 in the region where the drain electrode is to be formed.
A drain electrode layer 23d consisting of the aluminum metal layer 22d and the aluminum metal layer 22d is formed at the same time. Since the electrode metal layer formed on the photoresist film is not desired, it is lifted off and removed to complete the MES FET.

Note that the lower metal layer directly connected to the active layer or the Ge thin film in the electrode metal layer is not limited to titanium, and may be a high melting point metal such as W or Ta.

Further, in the above embodiment, the case where an n ⁺ layer is provided in the source and drain regions has been described, but the n ⁺ layer is not necessarily required, and the effects of the present invention do not change in the slightest even in a structure without this n ⁺ layer.

Furthermore, in the above example, an AsSG film was used as the spacer thin film on the Ge thin film, and consideration was given so that As would be introduced into the Ge during the subsequent heat treatment, but the spacer thin film on the Ge thin film is not necessarily There is no need to include impurities that serve as donors for the molecule. However, in order to obtain high-performance transistors with good reproducibility, it is necessary to dope Ge at a high concentration and reduce the contact resistance with the source and drain regions. Therefore, it is desirable to use a thin film doped with impurities as in the above embodiment.

Further, the lift-off for forming the electrodes may be performed using only photoresist without using the spacer insulating film as described above.

Furthermore, the means for forming the active layer 12 is not limited to the ion implantation method, and for example, an epitaxial layer formed by the vapor phase growth method may be used.
The heat treatment of the thin layer may be performed under the same conditions as in the above embodiment.

〔Effect of the invention〕

According to this invention, the ohmic contact electrodes in the source and drain portions and the shot contact electrodes in the gate portion can be formed from the same metal at the same time, and an alloying process for forming ohmic contacts is not required. There is no AuGe ball-up that often occurs in this process, and an MES FET with smooth electrodes can be obtained.

Additionally, since the mask alignment precision required in the conventional MES FET manufacturing process is not required, it has the advantage of significantly improving productivity.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional shot barrier gate type field effect transistor, and FIGS. 2 to 7 show a method for manufacturing a shot barrier gate type field effect transistor according to an embodiment of the present invention in the order of steps. FIG. 11... Semi-insulating GaAs substrate, 12... Operating layer (12' injection layer), 13... CVD SiO ₂ film, 15...
... Source region formation area, 16... Drain region formation area, 17... Ge thin film, 18... As SG
Film, 21, 21g, 21s, 21d... Titanium metal layer, 22, 22g, 22s, 22d... Aluminum metal layer, 23, 23g, 23s, 23d...
... Electrode metal layer, 14, 19... Photoresist film.

Claims (1)

[Claims] 1. A step of forming an active layer on the main area of a high resistivity semiconductor substrate, a step of depositing a germanium thin film on the source and drain regions on the surface of the active layer, and a step of forming an active layer on the surface of the active layer including the germanium thin film. a step of laminating at least one layer of a spacer insulating film, a step of heat-treating the semiconductor substrate together with the spacer insulating film, and forming a first opening in the spacer insulating film corresponding to a region where a gate region is to be formed. There is also a step of sequentially or simultaneously forming second openings corresponding to the areas where the source and drain regions are to be formed, and a step of depositing at least one metal layer for an electrode from above the spacer insulating film, and forming second openings in the first openings. The step of simultaneously forming a gate electrode layer on the active layer exposed to the active layer and the source and drain electrodes in the second opening, and the step of removing the electrode metal layer deposited outside the desired area. A method for manufacturing a field effect transistor, characterized in that: 2. The method of manufacturing a field effect transistor according to claim 1, wherein the first layer of the spacer insulating film is an insulating film doped with an impurity that serves as a donor to germanium. 3. The method for manufacturing a field effect transistor according to claim 1, wherein the heat treatment is performed in an atmospheric gas containing As.