JPS6050968A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To obtain smooth electrodes while eliminating an alloying step by forming simultaneously with the same metal ohmic contact electrodes of source and drain regions and Schottky contacting electrode of a gate. CONSTITUTION:Si<+> ion implanted layer 12' is formed on the surface layer of a semi-insulating substrate 11, and with a laminated film of an SiO2 film 13 and a photoresist film 14 provided on a gate region as a mask Si<+> ions are implanted to a source forming region 15' and a drain forming region 16'. Then, Ge is implanted to the entire surface, a Ge film 17' is formed on the laminated film, Ge film 17 is formed on the regions 15', 16', and the film 13 is removed together with the films 14, 17'. Subsequently, the layer 12' between the regions 15' and 16' produced by the previous ion implantation is altered to an N type region 12 by As ion implantation, and the regions 15', 16' are altered to N type regions 15, 16. Then, a gate electrode 23g is formed on the region 12, source electrode 23s, 23d are formed on the regions 15, 16, and all of them are formed of a laminate of Ti and Al.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to field effect transistors, and more particularly to the structure of a Schottky barrier gate type field effect transistor suitable for high frequency operation and its manufacturing method.

[Technical background of the invention and its problems]

Gallium arsenide (GaAs) semiconductor devices have superior high speed performance compared to silicon semiconductor devices, and research and development thereof has been rapidly progressing in recent years. In particular, GaAs Schottky barrier gate field effect transistors ((L+AsM
BS FBT) is being put into practical use as a microwave device, and is also one of the most important devices as a main component of GaAs1C.

In order to improve the performance of the GaAs MES FBT, it is necessary to reduce parasitic resistance and capacitance as much as possible.

In particular, it is important to keep the channel series resistance of the source/gate electrode layer low.

However, in a 0aAs MES FET, for example, as shown in FIG. ) and an n+ implantation layer (4) in the drain region, and a gate electrode (5) is provided on the n-type semiconductor layer (2) sandwiched between both regions.

A source electrode, a pole (6), and a drain electrode (7) are provided in both regions, respectively. In the diagonal structure, it is necessary to take into account errors due to mask alignment in each photoetching technique, and due to the limitations of the photoetching technique, it is necessary to make the distance between the source and gate a certain degree large. Therefore, as described above, the series resistance is reduced by the n-type active layer (2), and even if the gate length is made submicron, the performance does not improve as expected in Wakkanai.

In addition, the source electrode (6) and the drain electrode (7) are usually
A gold-germanium (Au-Ge) alloy-based electrode is used, but this electrode is always formed using an alloy called an alloy.
This requires an alloying process between the electrode metal and the GaAs crystal. During this alloying process, the electrode metal often reacts non-uniformly, causing island-like aggregation (ball-up), which does not lower the contact resistance sufficiently, and also makes it difficult to form an electrode with a smooth surface. This has been a hindrance to the formation of integrated circuits (ICs) that use multiple MES FETs.

Also, of course, the metals used for the gate electrode, which forms a Schottky junction due to force, and the source and drain electrodes, which form ohmic contact, are different f! It was something like that.

[Purpose of the invention]

The present invention eliminates the drawbacks of conventional manufacturing methods and aims to provide a novel method for manufacturing Schottky barrier gate field effect transistors. According to this invention, the metal layer for the gate electrode and the metal layer for the source and drain electrodes can be formed of metal layers having the same structure and can be formed at the same time, so that the manufacturing process can be significantly shortened. , [Summary of the Invention] A method for manufacturing a field effect transistor according to the present invention includes:
forming an active layer on the main surface of the high resistivity semiconductor substrate;
a step of depositing a germanium thin film on the source and drain regions on the surface of the active layer; a step of laminating at least one layer of a spacer insulating film on the active layer surface including the germanium thin film; and a step of depositing the semiconductor substrate together with the spacer insulating film. a step of heat-treating, and a step of sequentially or simultaneously forming a first hole in the spacer insulating film corresponding to a region where a gate region is to be formed and a second hole corresponding to a region where a source and drain region is to be formed; Then, at least one metal layer for an electrode is deposited from above the spacer insulating film, a gate electrode layer is applied to the active layer exposed in the first opening, and a source and drain electrode is applied to the second opening. and a step of removing the electrode metal layer deposited outside the desired area, and further, the first layer of the spacer insulating film is made of germanium. It is an insulating film doped with impurities that serve as donors.

Further, the heat treatment is carried out in an ambient gas containing, for example, A and s.

(Example of the invention) This invention will be described below with reference to the drawings for each example.
Explain to L.

First, an acceleration energy of 1 is applied to the semi-insulating GaAs substrate (If).
SL ions (8i'') of lcln are selectively implanted at a dose of 3.5Xi (lcln) at 00 keV into the MBS FET formation region to form an implantation layer (12') (FIG. 2).

Next, a CVD5i02 film θ3) with a thickness of about 3000× and a photoresist film I with a thickness of about 1 μm are laminated, and this is used as an ion shielding mask to cover the area where the source region is to be formed (15'
) and the region (16') where the drain region is to be formed are selectively implanted. This ion implantation is performed in a multi-stage implantation in which Si+ is implanted at an acceleration energy of 120 keV and a dose of 2.5×10 cm, and then at 250 keV and a dose of 2.5×10 cr++. Next, germanium (Oe) (17) was applied from above the CVD 5in2 film 0; 3) used for the ion shielding mask and the 7 otresist film (141).
A Ge film (
17') on the regions where the source and drain regions are planned to be formed.
Form thin films (17) and (17) (Fig. 3).

Next, the 17 Ge films on the mask are removed by lift-off, and the CVD SiO2 film 0 is also removed (FIG. 4).

Next, arsenic-doped silicon dioxide film (As sag)
(1→ was annealed for 15 minutes at 850°C in an Ar gas atmosphere containing deposited LAs to a thickness of about 5000×, and the implantation A4 (12') and the n+ implantation layer in the regions where the source and drain regions were to be formed were (15') and (16') are activated to form an active layer θa, a source region (151) and a drain region (14i1) (FIG. 5).

Note that the above annealing also serves as a heat treatment performed after the formation of the Ge thin film as claimed in the claims, whereby Oe and GaAs react, and the AsSG film α
From then on, As is doped into the Ge thin film at a high concentration.

Next, a Fortresist film OI is deposited, and the gate is masked at a predetermined position sandwiched between the source and drain regions using a mask in which the gate, source, and drain patterns are integrally formed. After alignment, holes corresponding to the gate, source, and drain are formed by photoetching, and the underlying As5G film is etched through these holes to expose the I, GaAs, and Ge surfaces (FIG. 6).

Next, a titanium (Ti) metal layer is applied to a thickness of about 1000 mm, and then an aluminum (A-t) metal layer is applied to a thickness of #r 400 (1,
A gate electrode (23 g) consisting of a titanium metal layer (21 g) and an aluminum metal layer (22 g) is formed in the region where the gate electrode is to be formed, and a titanium metal layer is still formed in the region where the source electrode is to be formed. (21s) and an aluminum metal layer (22s), and a titanium metal layer (21d) in the region where the drain electrode is to be formed.
A drain electrode layer (23d) consisting of and an aluminum metal layer (22,+) is formed at the same time. Since the electrode metal layer formed on the odoresist film is not desired, lit-off is removed to complete the MF+S FIT.

In the electrode metal layer, the lower metal layer which is directly connected to the Ge thin film in the case of the active layer'=i is not limited to titanium, but may be a high melting point metal such as W or Ta.

In addition, in the above embodiment, n1 is used in the source and drain regions.
Although the case where a layer is provided has been described, an n+ layer is not necessarily required, and the effects of the present invention do not change in the slightest even in a structure without an n+ layer.

Furthermore, in the above example, an AsSG film was used as the spacer thin film on the Ge thin film, and the Ge
Although consideration was given to introducing As into the film, the spacer thin film on the Ge thin film does not necessarily need to contain impurities that serve as donors for Ge. However, in order to obtain high-performance transistors with good reproducibility, it is necessary to dope Oe at a high concentration to reduce contact resistance with the source and drain regions. Therefore, it is desirable to use a thin film doped with impurities as in the above embodiment.

Further, the lift-off for forming the electrodes may be performed using only photoresist without using the spacer insulating film as described above.

Furthermore, the means for forming the active layer (12) is not limited to the ion implantation method, and for example, an epitaxial layer formed by vapor phase growth may be used. In this case, the Ge thin layer is also heat-treated under the same conditions as in the above embodiment. good.

〔Effect of the invention〕

According to this invention, the ohmic contact electrodes in the source and drain parts and the Schottky contact VA7 pole in the gate part can be formed simultaneously using the same metal, and there is no need for an alloying process for forming ohmic contacts. In this process, there is no ball-up of AuOe, which had occurred, and a MES FET with smooth electrodes can be obtained.

Further, since the mask alignment accuracy required in the conventional manufacturing process of MBS FI13T is not required, there is also the advantage that the effect of improving productivity is remarkable.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional Schottky barrier gate field effect transistor, and FIGS. 2 to 7 are a cross-sectional view of a conventional Schottky barrier gate field effect transistor.
11...Semi-insulating GaAs substrate 12... Active layer (12' injection layer) )13...
cvn sho, film 15...Source region formation area 16...Dray/region formation area ■7...
GeR film 18...As5G film 21 (21g, 21s, 21d)...Titanium metal layer 22 (22g, 22s, 22d)...Aluminum metal layer 23 (23g, 23g, 23d)...・
...Electrode gold layer 14.19... Photoresist film Agent Patent attorney Mr. Inoue Figure 1 Figure 2 Figure 4 Figure 5 Figure/2 Figure 6/1 Figure 7

Claims (3)

[Claims] (1) A step of forming an active layer on the main surface of a high resistivity semiconductor substrate, a step of depositing a germanium thin film on the source and drain regions on the surface of the active layer, and an insulating layer for spacers on the surface of the active layer including the germanium thin film. a step of stacking at least one layer of a film; a step of heat-treating the semiconductor substrate together with a spacer insulating film; and a step of forming a first opening in the spacer insulating film in a manner corresponding to a region where a gate region is to be formed. a step of sequentially or simultaneously providing second openings corresponding to the area where the area is to be formed; depositing at least one metal layer for an electrode from above the insulating film for a spacer and exposing it to the first opening; The present invention is characterized by comprising the steps of simultaneously forming a gate electrode layer in the active layer and a source and drain electrode in the second opening, and removing the electrode metal layer deposited outside the desired region. A method for manufacturing a field effect transistor. (2) The method for manufacturing a field effect transistor according to claim 1, wherein the first layer of the spacer insulating film is an insulating film to which an impurity serving as a donor is added to germanium. (3) The method for manufacturing a field effect transistor according to claim 1, wherein the heat treatment is performed in an atmospheric gas containing As.