JPH0436464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for identifying the product name of a semiconductor highly integrated circuit element (LSI).

(b) Background of the technology In recent years, with the development of semiconductor technology, especially integration technology, it has become possible to provide a large number of circuit elements as a single LSI package. Traditionally, logic circuits for data processing include combinational circuit elements such as NAND and OR circuits, as well as sequential circuits such as latches, registers, and flip-flop circuits (FF) obtained by multiple combinational circuits. connected and configured.

(c) Prior art and problems Conventionally, logic circuits have been obtained by combining combinational and sequential circuits as described above, but in the past, where the degree of integration was not so high, combinational and sequential circuit elements were each implemented in small numbers of the same type. A wide variety of small-scale integrated circuit elements (SSI) and medium-scale integrated circuit elements (MSI), which realize a specific basic function by combining a small number of these, are integrated into an intermediate mounting unit, such as a wiring printed board. By configuring circuit functions, it was used as a means for realizing logic circuits in data processing devices and the like.

As the degree of integration increases, complex logic circuits such as microprocessors (MPUs) are now available in a single package that is compact, lightweight, and low cost, in addition to the circuit functions of the conventional wiring printed board level. Desired LSIs based on customers' special specifications, such as master slice LSIs, can now be provided in a short time. The configuration of logic circuits in such LSIs consists of a large number of combinational circuits and sequential circuits, but the combination of these circuits is increasing as the degree of integration increases.
is offered in a large variety of varieties.

In general, when testing this wide variety of LSIs,
Identification of LSI products is done by manual recognition, such as by visually reading the product name from a stamp.
As the variety of LSIs increases, manual management is becoming increasingly difficult. On the other hand, these LSI and LSI
In order to facilitate the diagnosis of devices that use a large number of FFs and to identify the location of failures, a function has been introduced into the logic circuit to read the data held by the FF (scan-out) and to write the expected data to any FF (scan-in). There is.

(d) Purpose of the Invention The purpose of the present invention is to identify the LSI for each LSI in order to solve the problems associated with identifying many types of product names in LSI.
At the design stage, the product name is prepared internally as an identification code in a part of the configuration circuit, and when the LSI product name is required, it is sent out using the same method as reading data by scan-out, so that it can be used as before. The purpose is to provide a means for obtaining the product name using electrical signals without manual intervention.

(e) Structure of the Invention The object of the present invention is to provide a flip-flop circuit element corresponding to a plurality of pits for displaying the device type name in a code, and a flip-flop circuit element in the plurality of flip-flop circuit elements, in a highly integrated circuit element constructed by integrating a plurality of integrated circuit elements. The device is provided with a means for selectively wiring each positive output terminal or inverting output terminal in accordance with the type name of the element when connecting the flip-flop circuit element, and connects the type name obtained by zero-resetting the flip-flop circuit element to the scan chain of the flip-flop circuit element. This can be achieved by providing a method for identifying the product name of a highly integrated circuit element, which is characterized in that it is obtained by performing a scan-out operation using an applied shift clock.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings.

The figure shows a block diagram of a method for identifying the product type of a circuit element according to an embodiment of the present invention. In the figure, 1 is a scan chain for displaying the product name, 2a to h are wiring sections for setting bit data of "1" and "0" corresponding to the product name, and 3 is a scan chain with the main logic circuit for system operation. It is. More FFa~
h and FF1-n are flip-flop circuits, respectively. Here, scan chain 1 applies 0 to the set inputs of FFa to h prior to scanning out the product name, for example, according to the zero reset operation executed when the power is turned on, so that the output of its positive output terminal Q becomes a low level. It is assumed that the setting is made to output "0".

On the other hand, the wiring portions 2a to 2h are set by wiring with the product name assigned at the time of design selected at the time of manufacturing.

Here, an example of a variety name is shown as 11000100 in 8 bits. In contrast to scan chain 1, in which all FFs 1 to n constituting normal scan chain 3 in the past are configured by taking out the output signal from its positive output terminal Q and connecting it to the data input of the upper FF, In scan chain 1, wiring section 2
Corresponding to the data to be output by a to h, depending on the case, output from Q or the inverted output terminal and output from the lower
It is applied to the data input of FF. Therefore lower FF
The data shifted from is output from
In this case, the bit data "1" and "0" are inverted when passing through FFa, c, f, and g, so FFa
For example, in 10100110 output from ~h,
Since there is no FF to be inverted before the output, the highest FFa of FFa to h remains "1", and the "0" of FFb is inverted by FFa and finally output as 1 to the outside.

Below, 1 in FFc is 0, 0 in FFd is 0, 0 in FFe is 0, 1 in FFf is 1, 1 in FFg is 0, and 0 in FFh.
is output as 0, and the product name by the blending units 2a to 2h is output as 11000100.

In this embodiment, the scan chain 1 that outputs the product type name is configured in this way, so that according to the shift clock of the scan-out operation performed to read the data held by the conventional FF, the product type of the circuit element is written at the end of the scan-out data. The name can be read out as an electrical signal. In addition, since the number of FFa to h selected by the wiring sections 2a to h of scan chain 1 is set to an even number, the data scanned in from the outside to scan chain 3 has "1" and "0" inverted. There is no problem because the data is shifted from the input of scan chain 1 without being changed, but when the number of data is odd, it is necessary to provide a separate inverting circuit element or invert the scan-in data so that even parity is achieved. In this example, the product name is 8 bits, but it goes without saying that it can be similarly implemented using any other arbitrary number of bits. Also FF
The increase in the number of FFs is due to the improvement in the degree of integration of the circuit elements that make up LSIs, so the increase in the number of FFs to 10 types does not pose much of a problem. On the other hand, the increase in the number of input/output terminals, which is subject to severe restrictions in one package, can be ignored since the conventional system operation scan-out terminals can be shared and the shift clock can also be used, as explained above.

Of course, if the number of input/output terminals is sufficient, a scan out of the scan chain 1 may be provided separately for displaying the product name. In this case scan chain 1
Since scan-in is not required for , scan-in is exclusive to scan chain 3.

(g) Effects of the Invention As explained above, according to the present invention, instead of the conventional method of manually managing the LSI product name, the product name is managed according to the shift clock signal applied when the LSI is scanned out. is obtained as an electrical signal, so not only can you test a single LSI, but even when multiple LSIs are mounted on an intermediate mounting unit such as a printed wiring board, you can electrically check each one in their mounted state without the need for manual labor. This is useful because high-speed processing in product name identification can be realized.

[Brief explanation of drawings]

The figure is a block diagram of a method for identifying the product type of a circuit element according to an embodiment of the present invention. In the figure, 1 is a scan chain for displaying the product name, 2 is a wiring section, 3 is a scan chain for system operation,
FFa-h and FF1-n are flip-flop circuits.

Claims (1)

[Claims] 1. In a highly integrated circuit element configured by integrating a plurality of elements, a flip-flop circuit element corresponding to a plurality of bits code-indicating the product type of the element, and each positive output terminal in the scan chain connection of the plurality of flip-flop circuit elements. Alternatively, it is provided with a means for selectively wiring the inverting output terminal in accordance with the type name of the element, and the type name obtained by zero-resetting the flip-flop circuit element is applied to the scan chain of the flip-flop circuit element to perform a scan-out operation by a shift clock. A method for identifying the product name of a highly integrated circuit element, characterized in that it can be obtained by: