JPS59210657A - Discriminating method of name of kind of circuit element - Google Patents

Abstract

PURPOSE:To make sure kinds rapidly and easily one by one by connecting a discriminating circuit consisting of a large number of FF circuits to a large number of LSIs and generating electric signals of ''1'' or ''0'' according to applied shift clock signals when the LSIs are scanned out. CONSTITUTION:Wiring sections 2a-2h for setting bit data of ''1'' or ''0'' in response to the names of kinds to be discriminated are formed to mutually opposite scan chains 1, and flip-flop circuits FFa-FFh are connected in series through the wiring sections. Flip-flop circuits FF1-FFn are also mounted to a scan chain 3 consisting of a main logical circuit for operation, the FFn and the wiring section 2a are connected, and scan-out results are scanned out from a positive output terminal Q for the FF1. Accordingly, electric signals of ''1'' or ''0'' corresponding to each LSI are generated, and the kinds of each LSI displayed by a large number of bit numbers are determined rapidly and easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for identifying the product name of a semiconductor highly integrated circuit element (LSI).

('b) Background of the Technology In recent years, with the development of semiconductor technology, especially integrated technology, a large number of circuit elements have come to be provided as a single LSI package. Traditionally, logic circuits for data processing have included combinational circuit elements such as NAND and OR circuits, and many sequential circuits such as latches, registers, and flip-flop circuits (FF) obtained by combining multiple combinational circuits. Consists of interconnected components.

(e) Prior art and problems Conventionally, logic circuits have been obtained by combining combinational and sequential circuits as described above, but in the past, the degree of integration was not so high, and in the past, combinational and sequential circuit elements were each implemented in small numbers of the same type. A wide variety of small-scale integrated circuit elements (SSI) and medium-scale integrated circuit elements (MSI), in which a small number of these are combined to realize a specific basic function, are assembled into circuit functions using an intermediate mounting unit, such as a wiring printed board. It was used as a means of implementing logic circuits in data processing devices and the like.

As the degree of integration improves, complex logic circuits such as microprocessors (MPUs) are now provided in a single package that is compact, lightweight, and low cost, in addition to the conventional wiring printed board level circuit functions. Slice LSI
The desired L based on the special specifications of the customer, as typified by
SI was provided in a short time. Like this L
The configuration of logic circuits in SI consists of a large number of combinational circuits and sequential circuits, and as the degree of integration increases, LSIs are provided in a large number of types.

When testing a large variety of LSIs, the LSI types are generally identified by manual recognition, such as by visually reading the type name on a stamped display, but as the number of LSI types increases, manual management is becoming increasingly difficult. . On the other hand, in order to facilitate the diagnosis of these LSIs and devices using a large number of LSIs and to point out the location of failure, data held by the FF is read out (scan out), and expected data is written to any F'F (scan out). In) functions are introduced into logic circuits.

(ψ Purpose of the Invention The purpose of the present invention is to provide a product name as an identification code in a part of the configuration circuit for each LSI at the LSI design stage, in order to solve the problems associated with identifying the many types of product names in LSIs. In addition, when the LSI type name is required, the LSI type name is sent using a method similar to data reading by scan-out, and the purpose is to provide a means for obtaining the type name by electric signal without manual intervention as in the past. It is.

(e) Structure of the Invention The object of the present invention is to provide a flip-flop circuit element corresponding to a plurality of bits for code displaying the product type name of the element and a plurality of flip-flop circuits in a highly integrated circuit element configured by integrating a plurality of elements. The device is provided with a means for selectively wiring each positive output terminal or inverted output terminal in accordance with the type name of the element when performing scan chain connection in the element, and the type name obtained by zero-resetting the flip-flop circuit element is connected to the flip-flop circuit element. This can be achieved by providing a method for identifying the product name of a highly integrated circuit element, which is characterized in that it is obtained by performing a scan-out operation using a shift clock applied to the scan chain of the device. - (f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

The diagram shows the product types of circuit elements in one embodiment of the present invention.
Wiring section for setting bit data of ``'''0'', 3
is a scan chain of main logic circuits for system operation. Furthermore, FFIIL-h and FFI-n are each flip-flop circuits. In this case, scan chain 1 is a product (prior to the scan out of Φ name, for example, according to the zero reset operation that is executed when the power is turned on, 0 is applied to the set inputs of FFa-h, and when the output of the positive output terminal Q is low level) Select it and set it by wiring.

Here, an example of a variety name is shown as 11.000100 in 8 bits. In the scan chain 1, all of F'FI~n that make up the normal scan chain 3 in the past are connected to their positive output terminals (the output signal is taken out from Q and sent to the upper FF).
Compared to the data input connected to 7 and agreed to,
In scan chain 1, depending on the case, the data to be output from hrV to the wiring section α is output from Q or the inverted output terminal (Q and applied to the data input of the lower FF'. Therefore, the data is shifted from the lower FF. The data is FFa, C9f in the FF output from Q.
When passing through 9g, the 1°""0 part of the bit data is inverted, so 101 is output from F F a - h, respectively.
In oo11o, for example, the highest Fl"a of FFa~h
Since there is no FF to reverse the output cloth, just use ＼゛1″FF.
60'' of b is inverted by FFa and finally output as 1 to the outside.

Hereinafter, 1 in FFc is output as O, 0 in FFd is output as o, and the FFe product name is output as 11000100.

In this embodiment, the scan chain 1 that outputs the name to the product A is configured in this way, so that the circuit element is placed at the end of the scanout chain according to the shift clock of the scanout operation performed to correct and output the data held by the conventional FF. It is possible to read out one person's orgasm as an electrical signal. Naoko\
Since the value of Q in Ji'a-h is set to an even number, the data to be externally scanned into scan chain 3 is 1″IT
011 is shifted from the input of scan chain 1 without being inverted, so when the number of It is necessary to refute the data. In this example, the variety name is set to 8 bits, but it goes without saying that it can be done similarly using any other number of bits. Furthermore, the increase in the number of FFs is due to the improvement in the degree of integration of circuit elements constituting LSIs, and an increase in the number of FFs does not pose much of a problem.

On the other hand, the increase in the number of input/output terminals in one package, which is subject to severe restrictions, can be ignored since the terminals are shared with scan-in/out terminals for conventional system operation, and the shift clock can also be used, as explained above.

Of course, if the number of input/output terminals is sufficient, a scan chain 1 scanout may be provided separately for displaying the product name. In this case, scan chain 1 does not require scan-in, so scan-in is exclusively for scan-in chain 3.

(g) As described in detail, according to the present invention, instead of the conventional method of manually managing the LSI product name, the product name is changed to an electrical signal according to the shift clock signal applied during scan-in/out of the LSI. As a result, not only can a single LSI be tested, but even when multiple LSIs are mounted on an intermediate mounting unit such as a printed wiring board, the mounting status can be electrically checked one by one, making it possible to identify the product type without labor. This is useful because high-speed processing can be achieved.

[Brief explanation of the drawing]

The figure is a block diagram of a method for identifying the product type of a circuit element according to an embodiment of the present invention. In the figure, 1 is a scan chain for displaying the product name, 2 is a wiring section, and 3 is a scan chain for system operation. FFa-h and FFI-n are flip-flop circuits. Shift resistance) 7 (7・y 7

Claims (1)

[Claims] In a highly integrated circuit element configured by integrating a plurality of elements, a flip-flop circuit element corresponding to a plurality of bits that code the element type name, and each positive output when connecting a scan chain in the plurality of flip-flop circuit elements. A means for selectively wiring a terminal or an inverted output terminal in accordance with the type name of the element is not provided, and the type name obtained by zero-resetting the flip-flop circuit element is connected to the scan chain of the flip-flop circuit element. A method for identifying the product name of a highly integrated circuit element, characterized in that the identification method is obtained by performing a system scan-out operation using an applied shift clock.