JPH04367044A - Cache memory - Google Patents

Abstract

PURPOSE:To read the data out of a cache memory at a high speed to an operation where the same address is read out of a CPU even after the data are written into a main memory by a bus master except the CPU. CONSTITUTION:A cache memory 2 is provided with a CPU side access port which reads or write the data to the address received from a CPU 1, and a main memory side access port which can read or write the data to a main memory 5 and at the same time inputs the corresponding address and data to update the data of its own when a bus master, e.g. a DMA controller 7 except the CPU 1 write the data into the memory 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly to a cache memory that allows a write address and write data to be input when a bus master other than a CPU writes to the main memory.

0002

[Prior Art] Conventionally, this type of cache memory is
When a data write operation is performed to the main memory from a bus master other than the PU, in order to maintain the consistency of data at the same address in the main memory and cache memory,
The main memory address to which data has been written is monitored, and if that address exists inside the cache memory, that address is invalidated, and when the CPU reads the same address, the data inside the cache memory is not output. Load data from main memory,
The CPU was always able to read the latest data.

0003

[Problems to be Solved by the Invention] The conventional cache memory described above invalidates the same address in response to a write operation to the main memory from a bus master other than the CPU. In response to a read operation to the same address, the cache memory does not output the internal data, but instead reads the correct data rewritten from the slow main memory and outputs it to the CPU, which leads to a decrease in CPU performance. This tendency is especially noticeable in multitasking systems where different programs are frequently downloaded by a bus master other than the CPU.

The object of the present invention is to eliminate the above-mentioned drawbacks and to
It is an object of the present invention to provide a cache memory that does not cause a drop in performance of a CPU even when a write operation to a main memory is performed from a bus master different from a PU.

[0005]

[Means for Solving the Problems] A cache memory of the present invention has a CPU side access port that reads or writes data to an address sent from the CPU, and a CPU side access port that can read or write data to a main memory. When a bus master other than the CPU writes data to the main memory, the main memory side access port inputs the address and data to update its own data.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The embodiment shown in FIG. 1 shows an example of a computer system configured using a cache memory according to the present invention, and includes a CPU 1 and a cache memory 2 according to the present invention.
, main memory 5, and DMA (Direct Memory Access) as a bus master other than CPU 1.
s) It comprises a controller 7 and a system bus including a system address bus 3, a system control bus 4 and a system data bus 6.

Next, the operation of this embodiment will be explained.

[0010] The CPU 1 performs read or write operations on the cache memory 2.

In the case of a read operation, when the address to be read exists within the cache memory 2, the CPU 1
can read data from the cache memory 2 at high speed.

When the address to be read does not exist within the cache memory 2, the cache memory 2 outputs the address to be read to the system address bus 3 and a control signal to the system control bus 4 to access the main memory 5. By reading the data via the system data bus 5 and outputting it to the CPU 1 to complete the read operation, and making the read data exist inside the cache memory 2,
Thereafter, when the CPU 1 reads this address, data can be output from the cache memory 2 at high speed without accessing the slow main memory 5.

In the case of a write operation, when the address to be written exists within the cache memory 2, the cache memory 2 updates its own data with the written data and at the same time also connects the system bus to the main memory 5. Start a light cycle via

When the address to be written does not exist within the cache memory 2, its own data is not updated;
Other operations are the same as when the address to be written exists within the cache memory 2.

The DMA controller 7, which is a bus master other than the CPU 1, can access the main memory 5 via the system bus when the cache memory 2 is not using the system bus.

When the DMA controller 7 performs a read operation, the cache memory 2 is not affected in any way. When the DMA controller 7 performs a write operation, the cache memory 2 receives an address from the system address bus 3 and tests whether the address exists inside the cache memory 2 or not. If the data exists, the data is taken from the system data bus 6 and the data corresponding to that address in the cache memory 2 is updated.

[0017]

As explained above, the present invention enables bus masters other than the CPU to update the cache memory by inputting the address and data of a data write operation to the main memory from the bus master other than the CPU. Even after the data write operation, data can be output from the cache memory at high speed in response to a read operation from the CPU to the same address.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

[Explanation of symbols]

1 CPU 2 Cache memory 3 System address bus 4 System control bus 5 Main memory 6 System data bus 7 DMA controller

Claims (1)

[Claims] [Claim 1] A CPU-side access port that reads or writes data to an address sent from the CPU, and a bus master that is capable of reading or writing data to the main memory and that allows a bus master other than the CPU to write data to the main memory. A cache memory comprising: a main memory side access port that updates its own data by inputting the address and data when the cache memory is accessed.