JPH04367279A - Manufacture of non-volatile memory - Google Patents

Abstract

PURPOSE:To avoid an increase in cell size. CONSTITUTION:Within the title manufacture of non-volatile memory, after the formation of an oxide film and a nitride film or a polysilicon film made spacer on the sidewall of the first gate electrode 4, an offset region S is selfmatchingly formed using the source 11 side of the spacer as a mask and then the second gate electrode 9 is formed on the region S thereby making the offset region S the channel part of the first gate electrode 4. Through these procedures, the increase in the cell size as well as the dispersion in the transistor characteristics can be avoided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile memory that can be highly integrated, and more particularly to a method for manufacturing a split gate structure EPROM or FLASH E2PROM.

0002

BACKGROUND OF THE INVENTION In a conventional memory of this type, when forming an ion implantation layer, after forming a select gate (SG) 41 as shown in FIG.
The implantation layer 44 was formed by implanting As ions 43 using the resist pattern 42 as a mask. However, S.G.
Since the channel portion 45 of 41 is covered with the resist pattern 42, it is difficult to reduce the cell size due to misalignment. Further, variations in SG transistor characteristics pose a problem.

0003

Means for Solving the Problems and Effects This invention provides a method for forming a spacer of an oxide film, a nitride film, or a polysilicon film on the side wall of a first gate electrode having a source and a drain on a semiconductor substrate, and then An offset region is formed in a self-aligned manner using the side as a mask, and a second gate electrode is formed on the entire surface of the semiconductor substrate including the first gate electrode and the offset region, thereby forming the offset region with the channel portion of the first gate electrode. This is a method of manufacturing a non-volatile memory, comprising: That is, in the present invention, the source diffusion layer is formed in a self-aligned manner.

0004

[Example] Examples will be described below. As shown in FIG. 1, a first polysilicon layer is laminated on a Si substrate 1 having a gate oxide film 1 of SiO2, a resist pattern 3 for forming a select gate (SG) is formed, and etching is performed. 1 gate electrode) 4 is formed. Next, a SiO2 film is laminated on the entire surface of the Si substrate, including SG4, and its sidewalls (spacers) 5a and 5b are formed using reactive ion etching (see FIG. 2).
. Subsequently, after forming a photoresist pattern 6, wet etching is performed using this as a mask to remove one sidewall 5b (see FIG. 3). Thereafter, As ions 7 are implanted to form an offset region S on the source side (see FIG. 4). At this time, the ion implantation layer 6a on the region S side
was formed in a self-aligned manner like the ion-implanted layer 6b on the opposite side to SG4. Then, a source 10 and a drain 11 are formed using a conventional method such as heat treatment (see FIG. 5). Finally, after removing the sidewall 5a,
A second polysilicon layer is laminated over the entire surface with an SiO2 insulating film 8 interposed therebetween to form a program gate (PG) (second gate electrode) (see FIG. 5). At this time, the offset region S becomes the channel portion of SG4. FIG. 6 is an equivalent circuit diagram of the memory thus formed. In this way, in this embodiment, the offset region S is formed on the source side of SG4, and this is used as the channel portion of SG4, so that it is possible to prevent an increase in cell size and variations in characteristics of the SG transistor due to misalignment, which conventionally occur.

[0005]

[Effects of the Invention] As described above, according to the present invention, an offset region is formed on the source side and this is used as a channel portion of the gate, so that it is possible to prevent an increase in cell size and variations in transistor characteristics due to misalignment. effective.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a first step of a manufacturing process in an embodiment of the present invention.

FIG. 2 is a configuration explanatory diagram showing the second step of the manufacturing process in the above embodiment.

FIG. 3 is a configuration explanatory diagram showing the third step of the manufacturing process in the above embodiment.

FIG. 4 is a configuration explanatory diagram showing the fourth step of the manufacturing process in the above embodiment.

FIG. 5 is a configuration explanatory diagram showing the fifth step of the manufacturing process in the above embodiment.

FIG. 6 is an equivalent circuit diagram in the above embodiment.

FIG. 7 is a configuration explanatory diagram showing a conventional example.

[Explanation of symbols]

2　Si substrate 4 SG (first gate electrode) 5a SiO2 film (spacer) 9 CG (second gate electrode) 11 Sauce S Offset area

Claims (1)

[Claims] 1. After forming a spacer of an oxide film, nitride film, or polysilicon film on the side wall of a first gate electrode having a source and drain on a semiconductor substrate, an offset region is formed in a self-aligned manner using the source side of the spacer as a mask. and a second gate electrode is formed on the entire surface of the semiconductor substrate including the first gate electrode and the offset region, thereby making the offset region a channel portion of the first gate electrode. manufacturing method.