JPH04368031A - Multiplexer - Google Patents

Abstract

PURPOSE:To simplify and miniaturize the circuit configuration by eliminating the need for a clock interrupt detection circuit and a changeover circuit. CONSTITUTION:A circuit generating a multiplexing clock CK2 based on a video signal clock CK1 consists of a clock generating circuit 34 employing a PLL, a clock control circuit 50 generating a stuff multiplex clock CK3 based on the multiplexing clock CK2 consists of a frequency divider 51 and an OR circuit 52, the frequency divider 51 is used to frequency-divide the multiplex clock CK2 to generate the multiplex clock CK3, the inversion output of the stuff multiplex clock and the video signal clock CK1 are ORed by an OR circuit 52 and its OR output is fed back to the frequency divider 51.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing device provided for multiplexing main information such as video information and accompanying sub-information such as audio information in, for example, an optical transmission device.

0002

2. Description of the Related Art Conventionally, the following devices are known as this type of device. FIG. 4 is a circuit block diagram showing its configuration.

In the figure, a video signal VS output from an image pickup device or a video recording device (not shown) is encoded by a video encoding circuit (V-COD) 1, and then sent to a multiplexer 3 together with its clock CK1. Multiple conversion circuit (MU
X) is input to 31. On the other hand, the audio signal AS accompanying the video signal VS is transmitted to the audio encoding circuit (A-COD) 2.
After being encoded, the signal is input to the stuff multiplex conversion circuit 32. In this stuff multiplex conversion circuit 32, the encoded audio signal AD is synchronized with the video signal clock CK1.
Stuff pulses are multiplexed on S. This stuff-multiplexed encoded audio signal ASS is input to the multiplex conversion circuit 31.

The multiplexing device 3 also has a clock extractor 33, and this clock extractor 33 generates a multiplexing clock CK2 whose frequency is N times higher than the video signal clock CK1. . This multiplexing clock CK2 is then supplied to the multiplex conversion circuit 31. In the multiplex conversion circuit 31, in synchronization with the multiplexing clock CK2 supplied from the clock extractor 33, the encoded audio signal AS is stuff-multiplexed with the encoded video signal VDS.
Multiplexing with S is performed, and the multiplexed data MD obtained thereby is supplied to, for example, a next-stage multiplexer.

By the way, in this type of device, the video signal V
Even if S is not input, there may be cases where it is desired to transmit the audio signal AS alone. However, in the conventional device described above, the multiplex conversion circuit 31 and the stuff multiplex conversion circuit 32 are operated in synchronization with the video signal clock CK1 and the multiplexing clock CK2 generated based on this clock. is not input, the audio signal AS
cannot be sent alone.

[0006] Conventionally, therefore, a device as shown in FIG. 5, for example, has been considered. This device uses a PLL (phase locked loop) as a clock extractor.
In addition to using the circuit 34, a clock control circuit 40 is provided, and the clock control circuit 40 generates the stuff multiplexing clock CK3 based on the multiplexing clock CK2 output from the PLL circuit 34. It is.

That is, in the PLL circuit 34, during a period when the video signal clock CK1 is input, a multiplexing clock CK2 with a frequency N times higher than the video signal clock CK1 is generated in synchronization with the video signal clock CK1. CK1
When the clock CK2 is turned off, it enters a free-running oscillation state and continues to generate the multiplexing clock CK2.

On the other hand, the clock control circuit 40 is, for example, shown in FIG.
As shown in FIG.
In addition to a frequency divider 41 that generates K3, a synchronization circuit 42, a clock interruption detection circuit 43, and a switching circuit 44 are provided. In the synchronization circuit 42, the stuff multiplexing clock CK3 output from the frequency divider 41 is synchronized with the video signal clock CK1. With such a configuration, during the period when the video signal clock CK1 is input,
The switching circuit 44 is set on the synchronization circuit 42 side, and as a result, the stuff multiplexing clock CK3 synchronized by the synchronization circuit 42 is supplied to the stuff multiplexing conversion circuit 32. On the other hand, when the video signal clock CK1 is disconnected, this disconnection is detected by the clock disconnection detection circuit 43, and the switching circuit 43 detects this disconnection.
4 is switched to the frequency divider 41 side. Therefore, the stuff multiplexing clock CK3 outputted from the frequency divider 41 is supplied to the stuff multiplexing conversion circuit 32.

Therefore, in such a device, even if the input of the video signal VS is cut off, the multiplexing clock CK2 and the stuff multiplexing clock CK3 are generated, so that the audio signal AS is not transmitted. It will be done.

0010

However, in such a conventional device, the clock control circuit 40 requires a clock disconnection detection circuit 43 and a switching circuit 44, which complicates the configuration of the clock control circuit and increases the circuit scale. There was a problem in that it became larger.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a multiplexing device that eliminates the need for a clock disconnection detection circuit and a switching circuit, thereby allowing the circuit configuration to be easily miniaturized. It is about providing.

0012

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a phase-locked loop circuit that generates a second clock for time division multiplexing based on a first clock synchronized with main information. A clock control circuit that generates a third clock for stuff multiplexing based on the second clock is composed of a frequency divider and an OR circuit, and this frequency division The frequency of the second clock is divided by the frequency divider to generate a third clock, and the clock corresponding to the third clock generated by the frequency divider and the first clock are logically divided by the logical sum circuit. It is configured to add the sum and feed back the OR output to the frequency divider.

[0013]

[Operation] As a result, according to the present invention, during the period when the main information is input, the divided clock synchronized with the first clock of the main information by the OR circuit is fed back to the frequency divider, On the other hand, during a period when the main information is not input, the frequency-divided clock passes through the OR circuit as it is and is fed back to the frequency divider. Therefore, there is no need to switch the clock input to the frequency divider depending on whether the main information is input or the input is disconnected, and as a result, a switching circuit and a clock disconnection detection circuit are not required. therefore,
The circuit configuration of the clock control circuit is greatly simplified and miniaturized.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit block diagram showing the configuration of a multiplexing device according to an embodiment of the present invention. In this embodiment, the video signal VS is handled as the main information, and the audio signal AS is handled as the sub information, and the frequency of the video signal clock CK1 is set to f0, and the frequency of the multiplexing clock CK2 is set to the above-mentioned video signal clock. A case where the frequency is set to 2f0, which is twice the frequency f0 of CK1, will be explained. Further, in FIG. 1, the same parts as in FIG. 5 are designated by the same reference numerals.

The clock control circuit 50 of this embodiment is composed of a D-type flip-flop 51 which constitutes a frequency divider by two, and an OR circuit 52 which constitutes a synchronous circuit. The D-type flip-flop 51 receives the multiplexing clock CK2 outputted from the PLL circuit 34 into the clock input terminal C, and
Clock CK3 for stuff multiplexing from non-inverting output terminal Q
is outputting. The OR circuit 52 takes the logical sum of the video signal clock CK1 and the inverted output output from the inverted output terminal (Q￣) of the D-type flip-flop 51, and
The OR output OS is supplied to the input terminal D of the D-type flip-flop 51.

With such a configuration, first, during the period when the video signal VS is input, the PLL circuit 34 generates a clock 2f0 which is twice as high as the video signal clock CK1.
is generated, and this clock is used as the multiplexing clock CK2.
The signal is supplied to the multiplex conversion circuit 31 as a signal. Further, in the clock control circuit 50, the inverted output of the D-type flip-flop 51 and the video signal clock CK1 are input to the OR circuit 52, and as a result, the clock OS synchronized with the video signal clock CK1 is input to the D-type flip-flop 51. It is input to terminal D. Therefore, the D-type flip-flop 51 outputs the frequency-divided-by-2 clock CK3 synchronized with the video signal clock CK1 as the stuff multiplexing clock. FIG. 2 shows the clock control circuit 50 at this time.
This shows the operation timing.

On the other hand, when the input of the video signal VS is cut off, the PLL circuit 34 enters a free-running oscillation state, and the clock CK2' generated by this free-running oscillation is used as a multiplexing clock in the multiplex conversion circuit 31. supplied to Also,
In the clock control circuit 50, since the video signal clock CK1 becomes "L" level, the OR circuit 52 becomes a through state, and the inverted output of the D-type flip-flop 51 is directly returned to the input terminal D of the D-type flip-flop 51. Supplied. Therefore, the D-type flip-flop 51 operates equivalently as a self-synchronous frequency divider, and as a result, the D-type flip-flop 51 receives the free-running clock CK2' output from the PLL circuit 34. A clock CK3' whose frequency is divided by two is output as a stuff multiplexing clock. FIG. 3 shows the operation timing of the clock control circuit 50 at this time.

As described above, in this embodiment, the clock control circuit 50 is composed of the D-type flip-flop 51 and the OR circuit 52, and the D-type flip-flop 51 controls the PLL.
The clock CK2 output from the circuit 34 is divided by two to generate the stuff multiplexing clock CK3, and the video signal V
When S is input, this stuff multiplexing clock CK3 is converted to the video signal clock CK by the OR circuit 52.
1, it is possible to eliminate the need for a switching circuit and a clock disconnection detection circuit from the clock control circuit. Therefore, the circuit configuration of the device can be simplified and downsized.

It should be noted that the present invention is not limited to the above embodiments. For example, in the above embodiment, the video signal clock C
The explanation has been given by taking as an example the case where the multiplexing clock CK2 having a frequency 2f0 that is twice the frequency f0 of K1 is generated, but the multiplexing clock CK having a frequency three times or more
It can also be applied when generating 2. In this case, it is necessary to change the configuration of the frequency divider of the clock control circuit, but this can be handled by increasing the number of connected stages of D-type flip-flops.

Further, in the above embodiment, the case where the audio signal AS is handled as the sub information has been explained as an example, but it is also possible to transmit character information, coded information, etc. in addition to the audio signal AS, and furthermore, the video signal VS may be transmitted. If the input is cut off due to a failure or the like, guidance information consisting of an audio signal or text data indicating this fact may be sent out. Further, as the main information, data or the like may be sent instead of the video signal.

In addition, various modifications may be made to the configuration of the clock control circuit, the configuration of the clock generation circuit, the information multiplex conversion circuit, the stuff multiplex circuit, etc. without departing from the gist of the present invention. can.

[0022]

[Effects of the Invention] As detailed above, according to the present invention, a phase-locked loop is used for the circuit that generates the second clock for time division multiplexing based on the first clock synchronized with main information. A clock control circuit that is composed of a clock generation circuit and generates a third clock for stuff multiplexing based on the second clock is composed of a frequency divider and an OR circuit, and this frequency divider is used to generate the third clock for stuff multiplexing based on the second clock. A third clock is generated by dividing the second clock, and the clock corresponding to the third clock generated by the frequency divider and the first clock are logically summed by the logical sum circuit. By configuring the OR output to be fed back to the frequency divider,
A clock interruption detection circuit and a switching circuit can be omitted, thereby providing a multiplexing device whose circuit configuration can be easily and miniaturized.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the configuration of a multiplexing device in an embodiment of the present invention.

FIG. 2 is a timing diagram showing one operation of the clock control circuit of the device shown in FIG. 1;

FIG. 3 is a timing diagram showing another operation of the clock control circuit of the device shown in FIG. 1;

FIG. 4 is a circuit block diagram showing an example of the configuration of a conventional multiplexing device.

FIG. 5 is a circuit block diagram showing another example of the configuration of a conventional multiplexing device.

FIG. 6 is a diagram showing the configuration of a clock control circuit of the device shown in FIG. 5;

[Explanation of symbols]

1... Video encoding circuit (V-COD), 2... Audio encoding circuit (A-COD), 3, 30, 300... Multiplexing device, 3
1... Multiple conversion circuit (MUX), 32... Stuff multiple conversion circuit, 33... Clock extractor, 34... PLL circuit, 40
, 50... Clock control circuit, 41... Frequency divider, 42... Synchronous circuit, 43... Clock disconnection detection circuit, 44... Switching circuit, 5
1...D type flip-flop, 52...OR circuit.

Claims (1)

[Claims] Claim 1: A multiplexing device for time-division multiplexing and transmitting main information and sub-information accompanying the main information, wherein the time-division multiplexing is performed based on a first clock synchronized with the main information. a phase-locked loop type clock generation circuit for generating a second clock for the first clock; and a third clock synchronized with the first clock based on the second clock generated by the clock generation circuit. a clock control circuit for generating a stuff pulse; a stuff multiplex conversion circuit for multiplexing a stuff pulse on the sub information in synchronization with a third clock generated by the clock control circuit; the main information; an information multiplexing conversion circuit for time-division multiplexing the stuffed sub-information obtained by the stuffing multiplexing conversion circuit in synchronization with the second clock generated by the clock generation circuit; The clock control circuit includes a frequency divider that divides the frequency of the second clock to generate a third clock, a clock corresponding to the third clock generated by the frequency divider, and the first clock.
1. A multiplexing device comprising: an OR circuit that ORs a clock with a clock and feeds back the OR output to the frequency divider.